Latch Circuit Timing with Shifted Metastable Voltage
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Solution Overview
Problem
Digital circuits often experience slow switching speeds due to metastable states, where the output signal remains at a midpoint voltage, preventing proper response to input signal transitions and limiting operating speed, especially in latch circuits with weak drive power.
Innovation Solution
The metastable state is shifted closer to one of the binary states by using a series combination of transistors with different electrical characteristics and a delay circuit to actuate the switching process, ensuring timely state changes and improved response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a digital circuit uses conventional switching design, then the circuit structure is simple, but the switching speed is slow due to metastable states
Solution Approach 1:
The switching circuit is divided into multiple stages: a first digital circuit that responds to the input signal, a delay circuit that delays the input signal, and a second digital circuit that responds to the delayed signal. This segmentation allows the circuit to progress through metastable states in a controlled manner, improving switching speed without excessive complexity
Solution Approach 2:
The delay circuit performs preliminary action by delaying the input signal before it reaches the second digital circuit. This ensures that the first digital circuit has sufficient time to transition through metastable states and reach a stable state before the second circuit begins its transition, thereby improving overall switching speed
2Duration of action of moving object
If the input signal transitions quickly between binary levels, then the circuit response time is reduced, but the circuit may never transition through the metastable state and fail to switch output
Solution Approach 1:
The delay circuit provides preliminary action by delaying the input signal to the second digital circuit, ensuring that even when the input signal transitions quickly, the first digital circuit has adequate time to complete its metastable state transitions before the second circuit responds
Solution Approach 2:
The cross-coupled connection between the first and second digital circuits creates a feedback mechanism that ensures reliable state switching. The output of one circuit feeds back to the input of the other, maintaining synchronization and ensuring that metastable transitions are properly propagated even with short input signal durations
3Power
If one digital circuit has weak drive power when receiving input signal at metastable state, then the circuit design is simpler, but the latch switching response time becomes excessive
Solution Approach 1:
The latch circuit is segmented into two digital circuits with cross-coupled connections, allowing the switching action to be distributed across two stages. This segmentation enables each circuit to contribute to the overall switching action, improving response time even when individual circuits have weak drive power during metastable states
Solution Approach 2:
The cross-coupled configuration maintains continuity of useful action by ensuring that as one circuit transitions through its metastable state, the other circuit is already prepared to complete the switching action. This continuous action reduces the overall latch switching response time despite weak drive power conditions
Data Source
AI summary
Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.