Latch Multiplexer Circuit for Low-Noise, Low-Power Data Interleaving
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Solution Overview
Problem
Existing multiplexers negatively impact other circuitry in terms of noise and power performance, and are inefficient in terms of circuit area, particularly in digital-to-analogue converter (DAC) and analogue-to-digital converter (ADC) applications.
Innovation Solution
A latch circuit design that uses pairs of input switches to control currents and determine which current is larger, allowing for efficient multiplexing by synchronizing input information signals with a clock signal and operating in alternating setup and evaluation phases, thereby minimizing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional multiplexers are used to multiplex data signals, then the multiplexing function is achieved, but noise and power performance deteriorate and circuit area efficiency decreases
Solution Approach 1:
The multiplexer is segmented into multiple latch circuits, each handling a portion of the multiplexing task. Each latch circuit processes a subset of input signals independently, allowing parallel operation that reduces overall noise and power consumption while maintaining high multiplexing efficiency
Solution Approach 2:
The latch circuits operate in alternating setup and evaluation phases synchronized with a clock signal. During setup phase, inputs are prepared; during evaluation phase, the multiplexed output is generated. This periodic operation reduces instantaneous power consumption and noise compared to continuous operation in conventional multiplexers
2Productivity
If conventional multiplexer circuitry is implemented, then data multiplexing is achieved, but circuit area efficiency is reduced
Solution Approach 1:
Multiple latch circuits are merged into a single integrated multiplexer structure where shared components (such as clock distribution networks and output buffers) serve multiple functions. This consolidation reduces the total circuit area required compared to implementing separate multiplexer circuits
Solution Approach 2:
The latch circuits are designed with multi-functional capabilities, where the same circuit structure can handle different input signal combinations and operating conditions. This universality reduces the need for dedicated circuitry for each multiplexing scenario, thereby reducing overall circuit area
3Speed
If parallel current paths are used in latch circuit, then multiplexing speed is improved, but power consumption increases
Solution Approach 1:
The parallel current paths in the latch circuit are activated periodically rather than continuously. During the evaluation phase, multiple current paths operate in parallel to enable fast multiplexing; during the setup phase, these paths are deactivated or placed in low-power mode, reducing average power consumption while maintaining high speed when needed
Data Source
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AI summary
There is disclosed herein multiplexer circuitry. In particular, there is disclosed a latch circuit for use as a multiplexer to multiplex information carried by respective pairs of input information signals onto an output information signal, each pair of input information signals comprising a first input information signal and a second input information signal, and each pair of input information signals carrying information values based on signal values of those input information signals and interleaved with information values carried by the other pair or pairs of input information signals.