Latch-Offset Phase Detector for Stable DPLL Bandwidth
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Solution Overview
Problem
Conventional digital phase locked loops using bang-bang type phase detectors experience changes in gain due to jitter in the reference clock signal, leading to variations in bandwidth, which increases circuit area and power consumption due to the need for delay lines to maintain constant bandwidth.
Innovation Solution
A phase detector and phase-frequency detector with a latch circuit and initial voltage control circuit, where the initial voltage of the latch circuit is controlled by a control signal, mimicking the effect of jitter on the reference clock signal without the need for delay lines, using an offset controller with a sigma-delta modulator to generate a control signal that adjusts the initial voltage, thereby stabilizing the bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a delay line is added to maintain constant bandwidth in a digital phase locked loop using a bang-bang type phase detector, then the bandwidth stability is improved, but the circuit area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the delay line component from the phase locked loop system. Instead of using a delay line to add jitter to the reference clock signal, the invention uses the inherent jitter of the reference clock signal directly, thereby removing the unnecessary circuit component while maintaining bandwidth stability
Solution Approach 2:
The patent creates a simulated jitter effect by using the initial voltage control circuit to generate voltage variations that mimic the effect of delay line-induced jitter. This copying approach allows the system to achieve the same bandwidth stabilization effect without the physical delay line component
2Stability of the object's composition
If a delay line is added to maintain constant bandwidth in a digital phase locked loop using a bang-bang type phase detector, then the bandwidth stability is improved, but the power consumption increases
Solution Approach 1:
The patent extracts and eliminates the delay line component from the phase locked loop system. Instead of using a delay line to add jitter to the reference clock signal, the invention uses the inherent jitter of the reference clock signal directly, thereby removing the unnecessary circuit component while maintaining bandwidth stability
Solution Approach 2:
The patent enables the reference clock signal to serve its own jitter characteristic for bandwidth stabilization purposes. The inherent jitter in the reference clock signal is utilized directly to control the initial voltage of the latch circuit, eliminating the need for additional power-consuming jitter generation circuits
3Measurement precision
If the gain of the bang-bang type phase detector changes due to jitter in the reference clock signal, then the phase detection capability is affected, but the bandwidth of the phase locked loop changes
Solution Approach 1:
The patent applies preliminary action by controlling the initial voltage of the latch circuit before the phase detection process. The initial voltage control circuit adjusts the starting voltage level based on the jitter characteristics, preparing the system in advance to maintain consistent gain and bandwidth throughout the phase detection operation
Solution Approach 2:
The patent changes the voltage parameter of the latch circuit dynamically. By adjusting the initial voltage level in response to jitter conditions, the system maintains optimal operating parameters for phase detection while stabilizing the overall bandwidth of the phase locked loop
Data Source
AI summary
A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.