Cross-Coupled Latch Circuit for Parasitic Coupling Isolation
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Solution Overview
Problem
Conventional latches in digital electronics face challenges in efficiently storing data due to parasitic capacitive coupling, which can lead to signal interference and instability, especially when sharing components with other latches.
Innovation Solution
The design incorporates cross-coupled invertors and a specific configuration of transistors, including pull-up and pull-down transistors, to control the latch's operation and prevent parasitic capacitive coupling by enabling and disabling transistors based on input signals, thereby isolating input terminals and maintaining data stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional latch configurations are used to store data, then the latch can maintain two stable states, but parasitic capacitive coupling causes signal interference and instability
Solution Approach 1:
The patent introduces a coupling unit with decoupling transistors as an intermediary between the first and second invertors. This intermediary blocks parasitic capacitive coupling paths while allowing controlled signal transmission, thereby eliminating the harmful coupling effect without removing the fundamental latch structure
Solution Approach 2:
The patent extracts and removes the parasitic coupling paths by introducing decoupling transistors that open the coupling paths during latching operation. This separates the harmful capacitive coupling from the functional signal transmission, allowing the latch to maintain stability
2Device complexity
If transistors are shared between multiple latches to improve integration, then device complexity is reduced, but signal interference increases due to parasitic coupling
Solution Approach 1:
The coupling unit acts as a mediator that enables safe sharing of transistors between multiple latches. By controlling the decoupling transistors, the patent allows shared transistors to be used by multiple latches while preventing parasitic coupling interference, thus enabling integration without signal interference
3Stability of the object's composition
If the latch uses cross-coupled invertors for data storage, then two stable states are achieved, but parasitic capacitive paths cause instability
Solution Approach 1:
The patent converts the harmful parasitic capacitive paths into a controlled feature by using decoupling transistors to manage them. The same capacitive paths that cause interference are utilized for signal transmission when properly controlled, turning the harmful effect into a manageable aspect of the circuit operation
Solution Approach 2:
The decoupling transistors in the coupling unit serve as intermediaries that control the parasitic capacitive paths. They block these paths during latching to prevent instability while allowing controlled signal transmission, thereby maintaining state stability despite the presence of inherent parasitic capacitances
Data Source
AI summary
A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.