Memory Plane Latch Parity Storage to Free Cache Capacity

The patent extracts parity information storage from cache memory to unused latches in the memory device. By moving parity storage to a different location (latches instead of cache), the system maintains data protection while freeing up cache memory for other functions. This is achieved by calculating parity information and storing it in unused latches during write operations, then retrieving it from latches during read operations.

The patent introduces unused latches as an intermediary storage mechanism between the memory array and cache memory. These latches serve as a mediator that holds parity information temporarily during write operations and provides it during read operations, eliminating the need to occupy cache memory for parity storage while still ensuring data protection.

The patent implements periodic action by transferring parity information during programming periods using an interleaving scheme. The memory device alternates between storing data in latches and transferring parity information to the memory array, creating a periodic pattern that reduces latency by keeping the critical path busy without stalling for parity operations.

The interleaving scheme maintains continuity of useful action by overlapping parity transfer operations with data programming operations. Instead of sequentially completing all data writes before transferring parity, the system continuously performs both operations in an interleaved manner, maximizing resource utilization and reducing overall latency.