Memory Latch Parity Generation for Buffer-Limited NAND Arrays
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Solution Overview
Problem
The increasing complexity of redundant array encoding operations in memory systems due to higher failure rates in multi-layered NAND memory devices, leading to limited buffer space for parity data storage and potential user data loss.
Innovation Solution
Utilizing latches within the memory device to perform logical operations, such as XOR, for generating parity data, thereby reducing the burden on the memory controller's buffer and enhancing storage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant array encoding operations are performed using memory controller buffers, then parity data can be generated for error correction, but the buffer space becomes limited and storage performance deteriorates
Solution Approach 1:
The patent extracts the parity data generation function from the memory controller and relocates it to the memory device itself. Specifically, the memory device performs XOR logical operations internally using its own resources, separating the encoding function from the control logic and eliminating the buffer space requirement in the memory controller.
Solution Approach 2:
The memory device serves itself by performing redundant array encoding operations internally. The memory device uses its own logical operation circuits to generate parity data from incoming data, and stores both the data and parity data within its own structure, making the system self-sufficient and eliminating dependency on external buffer resources.
2Reliability
If more buffer space is allocated for parity data in the memory controller, then user data loss can be prevented, but additional space demand increases and device complexity rises
Solution Approach 1:
The patent removes the buffer space requirement from the memory controller by extracting the parity data storage function and placing it within the memory device structure. This eliminates the need for additional buffer resources in the control unit while maintaining data loss prevention capabilities.
Solution Approach 2:
The memory device structure is designed to serve multiple functions: it stores user data, generates parity data through internal logical operations, and stores the generated parity data within its own architecture. This multi-functionality eliminates the need for separate buffer resources dedicated solely to parity storage.
3Reliability
If redundant array encoding operations are performed in the memory controller, then parity data can be generated, but the operational burden increases and processing time is extended
Solution Approach 1:
The patent performs the logical operation of parity data generation simultaneously with the data writing operation. As data is being written to the memory device, the device concurrently performs XOR operations to generate parity data, which is then stored in the same operation cycle. This preliminary and concurrent action eliminates the need for separate encoding time after data writing.
Data Source
AI summary
Examples of the present disclosure provide a memory system and operating method thereof, and storage medium; wherein the memory system includes: a memory controller configured to send a first command, the first command including first data; and a memory device including a latch; the memory device coupled to the memory controller and configured to: receive the first command; in response to the first command, perform a logical operation on the first data with the latch to obtain parity data.