Latch-Based Phase Detection for Duty-Cycle-Independent Timing
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Solution Overview
Problem
Existing phase detectors in high-speed electronic devices and telecommunication systems face challenges in providing fast and accurate phase difference detection, especially with increasing operation frequencies and precision requirements.
Innovation Solution
A phase detector design incorporating a first latch and a control circuit that generates phase indicating signals by filtering out specific phase information from input signals, allowing for quick determination of phase differences based on rising and falling edges, independent of duty cycle deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase detectors are used to detect phase difference between input signals, then phase detection function is provided, but the detection speed is slow and accuracy is insufficient for high-speed electronic devices
Solution Approach 1:
The phase detector is segmented into multiple independent paths: a first path processes rising edges to generate first output signals, while a second path processes falling edges to generate second output signals. This segmentation allows parallel processing of different edge types, improving detection speed without sacrificing accuracy in high-speed applications
Solution Approach 2:
The latch circuit performs preliminary action by capturing and holding the phase difference information at the moment it occurs. The latch generates output signals that immediately reflect the phase relationship between input signals, enabling fast response and accurate detection simultaneously by preparing the output state in advance
2Reliability
If phase detectors process both rising and falling edges to provide comprehensive phase information, then complete phase difference data is obtained, but the output signal becomes unstable due to duty cycle deviations
Solution Approach 1:
The control circuit extracts only the necessary phase information from the output signals while discarding redundant information caused by duty cycle variations. By taking out only the relevant phase difference data and filtering out duty cycle-related fluctuations, the circuit achieves stable output signals without losing essential phase detection capability
Solution Approach 2:
The control circuit acts as an intermediary between the latch outputs and the final phase detection result. It mediates the signals by filtering out duty cycle deviations while preserving the essential phase difference information, thereby stabilizing the output without complete information loss
3Measurement precision
If multiple clock cycles are used for phase detection to ensure accuracy, then detection precision is improved, but the response time increases which is unacceptable for high-speed applications
Solution Approach 1:
The latch circuit performs preliminary capture of phase difference information in a single clock cycle, holding the state until the next detection event. This preliminary action eliminates the need for multiple averaging cycles, achieving both high precision and fast response by preparing the measurement result in advance
Solution Approach 2:
The detector rushes through the phase detection process in a single clock cycle by directly latching the phase difference information without iterative refinement. This skipping of multiple cycles maintains precision through the latch's inherent stability while dramatically reducing response time for high-speed applications
Data Source
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AI summary
A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.