Latch Polarity Inversion for Logic Delay Reduction
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Solution Overview
Problem
In synchronous logic designs, maintaining signal polarity across latch boundaries leads to inefficient use of inverters and logic gates, resulting in extra path delay and circuit power consumption.
Innovation Solution
A method is introduced to analyze synthesized logic, identify patterns for reduced inverters and latches in reversed polarity, and apply DeMorgan's Theorems to modify logic functions, optionally excluding certain latch paths and re-synthesizing the design to eliminate unnecessary logic gates, while ensuring no timing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal polarity is maintained across latch boundaries, then logic function correctness is ensured, but the number of inverters and logic gates increases leading to extra path delay and power consumption
Solution Approach 1:
The patent applies latch polarity inversion to change the signaling convention from positive-edge triggered to negative-edge triggered latches. By inverting the latch polarity, the signal polarity across latch boundaries is naturally inverted, which eliminates the need for additional inverters and logic gates that would otherwise be required to maintain correct logic function. This inversion principle directly resolves the contradiction by reducing path delay while preserving logic correctness through a fundamental change in the latch operation mode.
Solution Approach 2:
The patent changes the parameter of latch polarity (from positive to negative edge-triggered) to optimize the logic design. By modifying this parameter, the need for additional inverters and logic gates is eliminated, thereby reducing path delay and power consumption while maintaining logic function correctness. The parameter change approach allows the system to achieve better performance without compromising reliability.
2Reliability
If signal polarity is maintained across latch boundaries, then logic function correctness is ensured, but the number of inverters and logic gates increases leading to higher circuit power consumption
Solution Approach 1:
By inverting the latch polarity from positive-edge to negative-edge triggered, the patent eliminates the need for additional inverters and logic gates that would be required to maintain signal polarity across latch boundaries. Since inverters and logic gates consume power, removing them directly reduces circuit power consumption while the inverted latch polarity ensures logic function correctness is maintained.
Solution Approach 2:
The patent changes the latch polarity parameter to optimize power consumption. By switching from positive-edge to negative-edge triggered latches, the design eliminates unnecessary logic elements, thereby reducing the overall power consumption of the circuit while maintaining functional correctness.
3Loss of time
If latch polarity is inverted to reduce logic gates and delay, then path delay and power consumption are reduced, but timing violations may occur
Solution Approach 1:
The patent employs a feedback mechanism through a two-phase optimization process. In the first phase, latch polarity inversion is applied to reduce logic gates and delay. In the second phase, timing analysis is performed to detect any timing violations. If violations are detected, the design is adjusted to eliminate them. This feedback loop ensures that the optimization does not compromise timing requirements, resolving the contradiction between reducing path delay and maintaining timing reliability.
Solution Approach 2:
The patent performs preliminary timing analysis after latch polarity inversion to identify and correct potential timing violations before finalizing the design. By conducting this check in advance, the patent ensures that the optimized design meets timing requirements, preventing reliability issues from arising.
Data Source
AI summary
A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.