Latch Race Condition Resolution in Hardware Emulation
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Solution Overview
Problem
In hardware emulation, race conditions caused by differing propagation delays of signals to latch primitives lead to unwanted and uncontrollable behavior of the design under test, necessitating techniques to identify and prevent these conditions without increasing the design area.
Innovation Solution
A method and system that transform the hardware verification system to disable latch evaluation for a predetermined period, inject a new signal value, and enable evaluation based on a common en_group signal, ensuring stable clock values and reducing nondeterministic outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If auxiliary storage elements are added to resolve latch race conditions, then reliability is improved, but device complexity increases
Solution Approach 1:
The invention changes the timing parameters of latch evaluation by introducing a control signal (en_group) that enables or disables latch evaluation based on the stability of clock signals. Instead of adding storage elements, it modifies the evaluation timing parameter to prevent race conditions.
Solution Approach 2:
The invention introduces an intermediary control mechanism (en_group signal generation logic) that mediates between the clock signals and latch evaluation. This intermediary monitors clock signal stability and controls latch evaluation timing, resolving race conditions without adding auxiliary storage elements.
2Productivity
If latch evaluation is continuously enabled, then productivity is improved, but reliability deteriorates due to race conditions
Solution Approach 1:
The invention implements periodic control of latch evaluation by enabling evaluation only during stable clock periods. The en_group signal periodically enables latch evaluation when clock signals are stable and disables it during unstable periods, ensuring both productivity and reliability.
Solution Approach 2:
The invention performs preliminary action by generating the en_group control signal in advance based on clock signal stability detection. This preliminary control signal prepares the latches for safe evaluation before clock signals become unstable, preventing race conditions while maintaining continuous operation.
Data Source
AI summary
A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first code representing a first design including a first latch configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. The method further includes changing, using the computer, the first code into a second code representing a second design, the changing further including transforming, using the computer, the first latch into a second latch configured to be evaluated in accordance with a second signal different from the first signal after the first signal is received at the second latch, when the second code for the second design is compiled for programming into the hardware verification system.