Latch Reset Circuit for Floating-Node Delay Control
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Solution Overview
Problem
In high-speed mixed signal circuitry, latch circuits experience variable delays that can impact performance and introduce noise and distortion due to floating nodes when the clock signal is inactive, especially in applications like data converters.
Innovation Solution
A latch circuit with a reset circuit that maintains inter-latch nodes at a predetermined voltage level when the clock signal is inactive, using transistors gated by the data and clock signals, and additional switches to prevent floating voltages, ensuring consistent operation and minimizing data-dependent delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a latch circuit is used in high speed switching circuitry, then the circuit can operate at high speeds, but variable delay from floating nodes causes performance degradation and noise
Solution Approach 1:
The reset circuit proactively maintains inter-latch nodes at a predetermined voltage level during the inactive clock phase, before the next active phase begins. This preliminary action prevents floating voltage conditions that would otherwise cause variable delays and performance degradation, ensuring consistent latch operation at high speeds.
2Use of energy by moving object
If the clock signal is inactive, then power consumption is reduced, but inter-latch nodes float causing data-dependent delays
Solution Approach 1:
The reset circuit acts as an intermediary component that actively maintains inter-latch nodes at a predetermined voltage level during the inactive clock phase. This intermediary action prevents floating voltage conditions without requiring full circuit operation, thereby minimizing data-dependent delays while maintaining acceptable power consumption during idle periods.
3Reliability
If a reset circuit is added to maintain predetermined voltage levels, then floating nodes are eliminated and delay consistency improves, but circuit complexity increases
Solution Approach 1:
The reset circuit applies localized voltage maintenance only to specific inter-latch nodes that would otherwise float during the inactive clock phase. Rather than resetting the entire latch circuit, this local quality approach targets only the problematic nodes, eliminating floating conditions and improving delay consistency with minimal additional complexity.
4Speed
If transistors are gated by data and clock signals, then switching speed is enhanced, but asymmetric turn-on and turn-off times cause non-linear distortion
Solution Approach 1:
The reset circuit applies a preliminary counteracting voltage to inter-latch nodes during the inactive clock phase, opposing the asymmetric voltage conditions that would otherwise cause non-linear distortion. This preliminary anti-action equalizes turn-on and turn-off times, eliminating distortion while preserving the high switching speed enabled by gated transistors.
Data Source
AI summary
In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.