Latch Scan Chain Reconfiguration for Compact Memory Testing
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Solution Overview
Problem
There is a trade-off between reducing the mounting area of semiconductor storage devices and improving fault detection rates, as using latch circuits instead of flip-flop circuits prevents effective scan testing.
Innovation Solution
A semiconductor device with first and second latch circuits and switch circuits that allow for operation in normal and test modes, enabling connection paths between data output and input terminals to facilitate scan testing while maintaining reduced mounting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If latch circuits are used instead of flip-flop circuits, then mounting area is reduced, but scan testing becomes impossible
Solution Approach 1:
The patent implements dynamic reconfiguration of the latch circuit by introducing a control signal that can switch the circuit between a normal operation mode and a scan test mode. In normal mode, the latch circuit functions as a standard storage element. In test mode, the control signal reconfigures the circuit to enable scan testing functionality, allowing the same hardware to adapt its behavior based on operational requirements.
Solution Approach 2:
The patent makes the latch circuit multi-functional by enabling it to perform both normal storage operations and scan testing functions using the same hardware structure. Through the control signal mechanism, the latch circuit can serve dual purposes: maintaining data storage functionality while also supporting test operations, thereby eliminating the need for separate test circuits.
2Reliability
If flip-flop circuits are used, then scan testing can be performed, but mounting area increases
Solution Approach 1:
The patent transforms the static latch circuit into a dynamic structure that can change its operational characteristics based on the control signal. This dynamic capability allows the circuit to exhibit flip-flop-like behavior during scan testing while maintaining latch circuit area efficiency during normal operation, effectively getting the benefits of both circuit types without the area penalty.
Solution Approach 2:
The patent merges the functionality of latch circuits and flip-flop circuits into a single unified structure. By combining the area efficiency of latch circuits with the scan testing capability of flip-flop circuits through control signal manipulation, the invention achieves both goals in one integrated circuit design.
Data Source
AI summary
A latch group includes a first latch circuit, a second latch circuit, and a third latch circuit. A clock signal of which a signal value is inverted from a clock signal of the second latch circuit is input to the first latch circuit and the third latch circuit. A control circuit is configured to operate the latch group in a normal mode, and first and second test modes. The control circuit, while operating the latch group in a first test mode, transmits a control signal to the first switch circuit to connect the electrical path between the first data output terminal and the second data input terminal, and while operating the latch group in the second test mode, transmits a control signal to the second switch circuit to connect the electrical path between the second data output terminal and the third data input terminal.