Latch-Based Scan Chain for Low-Cost Memory Array Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing technologies for testing integrated circuits, particularly memory ICs, face challenges due to the high cost of using conventional scan chains based on flip-flops, making it impractical to implement scan testing in large memory arrays.
Innovation Solution
The development of low-cost scan chain architectures using scannable latches, which require fewer transistors and allow for efficient testing of large memory arrays by using non-overlapping scan sub-clock pulses to sequentially update latches, enabling affordable scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan chains based on flip-flops are used for testing memory ICs, then testing capability is achieved, but cost increases significantly
Solution Approach 1:
The patent replaces expensive flip-flops with cheaper latches for scan chain functionality. Latches are simpler memory elements that can be implemented with fewer transistors, reducing the cost per scan element while maintaining the essential scan testing capability throughout the memory array.
Solution Approach 2:
The patent changes the fundamental parameter of the scan element from flip-flop to latch, exploiting the cost difference between these two memory elements. This parameter change enables scan testing in cost-sensitive applications where flip-flop-based scan chains would be prohibitively expensive.
2Ease of manufacture
If latches are used instead of flip-flops in scan chains, then cost is reduced, but timing control becomes more complex
Solution Approach 1:
The patent divides the scan chain into multiple independently controllable latch groups, each with its own control signals. This segmentation allows precise timing control of individual latch updates, managing the complexity of latch-based scan operations by breaking down the control mechanism into manageable segments.
Solution Approach 2:
The patent employs dynamic control signals that sequentially enable and disable different latch groups at different times during the scan operation. This dynamic timing control allows the system to manage latch updates in a coordinated manner, reducing the complexity burden of using latches instead of flip-flops.
Data Source
AI summary
A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem.A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.