Latch-Type Sense Amplifier for Scan Testing With Lower Overhead
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Solution Overview
Problem
Conventional scan techniques for integrated circuit testing require significant memory and test time, leading to large vector sets and inefficient area and power consumption.
Innovation Solution
A sense amplifier cooperates with a data output latch circuit to generate test results in test mode, eliminating the need for additional shadow latch circuits and optimizing area and power consumption by integrating a built-in self-test circuit with a DFT multiplexer and multiplexers to manage power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan techniques are used for integrated circuit testing, then testing functionality is achieved, but memory usage and test time increase significantly
Solution Approach 1:
The patent merges the scan chain functionality with the sense amplifier and output latch circuit, allowing these circuits to serve dual purposes: normal read operations and scan-based testing. This integration eliminates the need for separate shadow latch circuits dedicated solely to testing, thereby reducing memory usage while maintaining testing functionality.
Solution Approach 2:
The sense amplifier and output latch circuit are designed to perform multiple functions: they operate during normal read cycles to sense and latch data from memory cells, and during test mode to capture and output test results. This multi-functionality reduces the need for dedicated test-specific circuits, optimizing memory usage.
2Reliability
If conventional scan techniques are used for integrated circuit testing, then testing functionality is achieved, but test time increases significantly
Solution Approach 1:
By combining the scan chain with the sense amplifier and output latch, the patent enables test results to be captured and output through the existing high-speed read path infrastructure. This integration allows test data to be transferred at full memory bandwidth speeds rather than requiring separate, slower test-specific output paths, thereby reducing test time.
3Reliability
If shadow latch circuits are added for testing, then testing capability is improved, but area penalty increases
Solution Approach 1:
The patent merges the scan chain functionality with the sense amplifier and output latch circuit, allowing these circuits to serve dual purposes: normal read operations and scan-based testing. This integration eliminates the need for separate shadow latch circuits dedicated solely to testing, thereby reducing memory usage while maintaining testing functionality.
Solution Approach 2:
The sense amplifier and output latch circuit are designed to perform multiple functions: they operate during normal read cycles to sense and latch data from memory cells, and during test mode to capture and output test results. This multi-functionality reduces the need for dedicated test-specific circuits, optimizing memory usage.
4Reliability
If additional logic circuits are added for scan testing, then testing functionality is improved, but power consumption increases
Solution Approach 1:
The sense amplifier and output latch circuit are designed to perform multiple functions: they operate during normal read cycles to sense and latch data from memory cells, and during test mode to capture and output test results. This multi-functionality reduces the need for dedicated test-specific circuits, optimizing memory usage.
Data Source
AI summary
A device is provided and includes a sense amplifier and an output latch circuit. The sense amplifier adjusts voltage levels of first and second data lines according to a bypass data signal corresponding to a data signal in response to a first enable signal having a first logic state and a second enable signal having a second logic state different from the first logic state during a test mode. The output latch circuit generates a data output signal according to the voltage level of the first data line in response to the first enable signal having the second logic state and a third enable signal having the first logic state during the test mode.