Latch Storage Circuit Layout for Soft Error Resistance
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Solution Overview
Problem
As the degree of integration of integrated circuits increases, the capacitance at the storage node of latch circuits is reduced, leading to more soft errors due to unintentional changes in data stored in the latch circuit, often caused by cosmic rays.
Innovation Solution
A latch-based storage circuit is designed with a latch circuit, an access circuit, and a control circuit, featuring first to fourth transistor pairs and access transistors with different conductivity types, which are connected to storage nodes to write and read data bits while controlling voltage levels to prevent soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the degree of integration of integrated circuits is increased, then the area and size of the circuit are reduced, but the capacitance at the storage node is reduced leading to increased soft errors
Solution Approach 1:
The storage circuit is divided into multiple transistor pairs (first to fourth transistor pairs) with distinct functions. Each transistor pair is connected in series through storage nodes, creating segmented functional units that maintain stability while integrating closely. This segmentation allows each unit to contribute to error resistance without increasing overall area.
Solution Approach 2:
The circuit implements nested storage nodes where each storage node is connected to gates of transistors in adjacent stages. The first storage node connects to gates of transistors in the first and second pairs, the second storage node connects to gates of transistors in the second and third pairs, and so on. This nested connectivity pattern maintains strong signal coupling and capacitance effects within a compact integrated layout.
2Reliability
If a dual interlocked storage cell (DICE) latch circuit is used to improve soft error resistance, then reliability against soft errors is improved, but the circuit size and complexity increase
Solution Approach 1:
The circuit uses transistor pairs with different conductivity types (PMOS and NMOS) positioned at specific locations to create local functional differences. The first and third transistor pairs use one conductivity type while the second and fourth pairs use another, creating localized functional zones that achieve DICE-level error resistance without requiring the full complexity of a traditional DICE cell throughout the entire circuit.
Solution Approach 2:
The circuit merges the latch function, access circuit, and control circuit into a single integrated storage circuit unit. The latch circuit includes multiple transistor pairs that work together to provide both storage and error resistance functions simultaneously, eliminating the need for separate DICE cell implementation and reducing overall circuit complexity.
3Productivity
If access transistors with different conductivity types are used to write and read data bits, then write and read operations are improved, but the transistor count and layout complexity increase
Solution Approach 1:
The access transistors with different conductivity types serve multiple functions: they enable both write operations (by controlling data input to storage nodes) and read operations (by enabling data output from storage nodes). The first access transistor with first conductivity type and the second access transistor with second conductivity type work together to provide universal access functionality, reducing the need for separate write and read transistor sets and simplifying the overall layout.
Data Source
AI summary
A storage circuit includes a multi-stage latch circuit having first to fourth transistor pairs therein, which respectively include a pull-up transistor and a pull-down transistor connected in series through a corresponding one of first to fourth storage nodes. An access circuit is provided, which has a plurality of access transistors of different conductivity type therein. The access transistors are electrically coupled to at least two of the first to fourth storage nodes and configured to enable writing of data bits into at least some of the first to fourth storage nodes, and reading of data bits from at least some of the first to fourth storage nodes. A control circuit is provided, which controls the access circuit during the writing and reading.