Latch Timing Analysis Isolation for Circuit Design
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Solution Overview
Problem
Existing methods for latch timing analysis in electronic circuits require a large number of iterations to converge, leading to increased computational resources and processing costs, especially in designs with latch loops.
Innovation Solution
The method involves building a timing graph of the circuit design, determining device and wire delays, performing clock and data arrival propagations, identifying latch loops, and prioritizing latch analysis within these loops to reduce iterative propagations across the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional latch timing analysis is performed on the entire circuit design, then complete timing verification is achieved, but the number of iterations and computational resources increase significantly
Solution Approach 1:
The patent segments the circuit design by identifying and isolating latch loops from the rest of the circuit. By separating the latch loop analysis from the general circuit analysis, the method performs targeted iterations only where needed (within latch loops) rather than throughout the entire circuit, thereby reducing the total number of iterations while maintaining verification completeness.
Solution Approach 2:
The patent extracts latch loops from the general circuit design and performs specialized analysis on them separately. This extraction allows the timing analysis to focus computational efforts on the most critical and problematic areas (latch loops that require multiple iterations) without repeatedly processing the entire circuit, thus improving convergence speed.
2Reliability
If latch analysis is performed on all latches sequentially, then comprehensive timing check is achieved, but processing time and computational cost increase
Solution Approach 1:
The patent performs preliminary identification and isolation of latch loops before conducting the full timing analysis. By pre-characterizing which latches are part of loops and which are not, the method can prioritize analysis efforts and perform preliminary computations that reduce the overall processing time while maintaining comprehensive timing checks.
Solution Approach 2:
The patent applies different analysis qualities and iteration counts to different parts of the circuit. Latch loops receive intensive analysis with multiple iterations, while non-loop latches receive simplified analysis with fewer iterations. This localized quality adjustment maintains comprehensive timing verification while significantly reducing overall processing time.
Data Source
AI summary
Performing timing analysis of a circuit design includes building a timing graph of the circuit design, and determining delays of devices and wires of the circuit design based on the timing graph. Further, clock and arrival propagations for the circuit design are performed based on the delays of the devices and wires, latch loops are identified in the circuit design, and latch analysis on latches of the latch loops is performed. The timing analysis further includes performing arrival propagation for circuit elements of the circuit design impacted by the latch analysis performed on the latches of the latch loops, performing latch analysis on latches of the circuit design external to the latch loops, and performing required time and slack calculations on the circuit design.