Latch Timing Circuit for Stable Low-Power Image ADCs
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Solution Overview
Problem
In solid-state imaging devices with built-in analog-to-digital converters, the time detection circuit faces challenges in maintaining resolution while reducing power consumption, and simultaneous operation of multiple converters can lead to malfunctions due to fluctuations in power supply voltage or ground potential.
Innovation Solution
A time detection circuit with a latch unit that operates based on startup and execution instructions, utilizing a signal path with a first logic element and a signal maintenance logic circuit to manage latch timing signals and prevent malfunctions during power fluctuations, ensuring normal operation and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the length of the time interval is shortened to reduce power consumption, then power consumption is reduced, but resolution of the AD conversion circuit is degraded
Solution Approach 1:
The latch unit operates periodically rather than continuously. It starts capturing the data signal only when the startup instruction signal is detected, and ends capturing when the execution instruction signal is input. This periodic operation reduces power consumption while maintaining measurement precision by concentrating operational activity into specific time windows.
Solution Approach 2:
The operational state of the latch unit is dynamically changed based on control signals. The latch unit transitions between active (capturing) and inactive (holding) states, allowing the system to adapt power consumption levels while preserving the captured data state through the hold function.
2Productivity
If multiple AD conversion circuits operate simultaneously, then productivity is improved, but malfunctions occur due to power supply voltage or ground potential fluctuations
Solution Approach 1:
The signal maintenance logic circuit proactively prevents malfunctions by maintaining the latch timing signal in a stable state during power fluctuations. When power supply voltage or ground potential fluctuates, the maintenance logic circuit ensures the latch unit does not inadvertently change state, preventing errors before they can occur during simultaneous operations of multiple converters.
Solution Approach 2:
The system prepares for potential power fluctuations by implementing a maintenance logic circuit that cushions against instability. This circuit absorbs the impact of power variations by maintaining the latch timing signal state, providing a buffer that protects against malfunctions during simultaneous converter operations.
3Measurement precision
If the frequency of the clock is increased to improve resolution, then resolution is improved, but power consumption increases
Solution Approach 1:
The latch unit operates periodically based on control signals rather than continuously at high frequency. This allows the system to use a lower clock frequency while achieving the same effective resolution by concentrating measurements into active periods, thereby reducing overall power consumption while maintaining precision.
Data Source
AI summary
A latch unit that starts an operation of capturing a data signal according to a startup instruction signal and holds the data signal and ends the capturing operation at a timing at which an execution instruction signal is input, a first signal path that transfers a latch timing signal as the startup instruction signal, and a second signal path that transfers the latch timing signal as the execution instruction signal are included, and a first logic element that outputs a first output signal switched to a logical value according to a logical value of an input signal at a first predetermined timing, and a signal maintenance logic circuit that continues to output a second output signal with a predetermined logical value according to the logical value of the input signal until initialization of a reset signal is indicated are arranged in the second signal path.