Global and Local Latch Timing for Collision-Free Memory Writes
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Solution Overview
Problem
In memory devices, collisions can occur when new address and data information is transmitted from global latches to local latches before previous write operations are complete, leading to increased device cycle time due to the extension of clock pulses.
Innovation Solution
Implementing local data and address latches controlled independently of global latches, using local clock signals to hold information longer and manage it separately, thereby avoiding collisions and reducing cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If new address and data information is transmitted from global latches to local latches before previous write operations are complete, then device cycle time increases due to extension of clock pulses, but data integrity is maintained
Solution Approach 1:
The latch system is divided into two independent segments: global latches for receiving data from external sources and local latches for distributing data to memory banks. Each segment operates with its own clock signal, allowing independent timing control. This segmentation enables the global latches to receive data on one clock edge while local latches distribute it on the opposite clock edge, eliminating the need to extend clock pulses and reducing device cycle time while maintaining data integrity.
Solution Approach 2:
The patent implements dynamic clock signal distribution where the global clock signal and local clock signal can be independently controlled in phase and timing. This dynamic control allows the system to optimize the timing of data transfer between global and local latches, preventing collisions without requiring fixed extended clock pulse widths, thereby reducing overall device cycle time while ensuring reliable data transfer.
2Productivity
If local latches are controlled independently with local clock signals, then collisions are avoided and operational efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges the global latch control and local latch control into a unified dual-latch architecture where both latch types share common data pathways and are coordinated through complementary clock signals. This merging approach allows independent control of global and local latches to prevent collisions while maintaining a standardized interface and control logic, avoiding the need for entirely separate control systems and thus limiting the increase in device complexity.
Data Source
AI summary
A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.