Voltage-Limiting Latch Transfer Circuit for Noise Immunity
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Solution Overview
Problem
High-speed logic circuits, such as latches and flip-flops, are prone to noise-induced errors due to unwanted signal propagation through parasitic capacitors, causing voltage drops or rises that can open transfer gates even when they are in a non-transparent mode, leading to incorrect data storage.
Innovation Solution
A voltage limiting transfer circuit is introduced between the input node and the latch, comprising pull-up and pull-down circuits that limit voltage levels to a predefined range during non-transfer modes, preventing unwanted signal propagation and ensuring that transistors do not conduct unnecessarily.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fast transfer gate is used to allow quick signal propagation, then the speed of the logic circuit is improved, but parasitic capacitors cause unwanted signal propagation even during non-transparent mode
Solution Approach 1:
A voltage limiting circuit is introduced as an intermediary between the transfer gate and the latch. This circuit includes a first voltage limiting element connected to the first node and a second voltage limiting element connected to the second node, which actively limit voltage excursions and prevent unwanted signal propagation while maintaining fast operation.
Solution Approach 2:
The voltage limiting elements are configured to preemptively counteract voltage excursions before they can cause unwanted transistor conduction. By establishing voltage thresholds in advance, the circuit prevents parasitic capacitive coupling from opening transfer gates during non-transparent mode.
2Reliability
If voltage limiting circuits are added to prevent noise-induced errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The voltage limiting elements modify the voltage parameters at critical nodes by clamping voltage excursions to predefined thresholds. This changes the electrical characteristics of the nodes to prevent unwanted transistor conduction while maintaining a relatively simple circuit structure.
Solution Approach 2:
Voltage limiting is applied locally at specific nodes where parasitic capacitive coupling occurs, rather than throughout the entire circuit. This targeted approach provides noise immunity where needed while minimizing overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise-induced errors by maintaining stable voltage levels, preventing incorrect data changes in the latch during non-transparent modes, and allowing faster operation than traditional circuits with logical gates.
Implementation Method 1
multiple transfer gates receive signals that were not intended to be provided to them (via parasitic capacitors also referred to as coupling capacitors)
Data Source
AI summary
A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.