Latch-Up Protection Circuit Layout for Stacked Semiconductor Packaging
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Solution Overview
Problem
The increasing integration and packaging density of semiconductor devices lead to a higher likelihood of latch-up events, which can cause irreversible damage due to parasitic silicon controlled rectifiers, necessitating improved layout designs or process technologies to enhance reliability.
Innovation Solution
Incorporating a latch-up protection circuit separated from the chip and utilizing redistribution layers to transmit signals, forming a hard block with a molding structure to surround and protect the chip from latch-up damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration and packaging density are increased, then productivity and device functionality are improved, but the likelihood of latch-up events increases due to parasitic silicon controlled rectifiers
Solution Approach 1:
The semiconductor device is divided into separate functional blocks: a first chip containing logic circuits and a second chip containing latch-up protection circuits. This segmentation physically separates the vulnerable logic circuits from potential latch-up sources, allowing high integration density on the first chip while maintaining latch-up resistance through the dedicated protection circuitry on the second chip.
Solution Approach 2:
A latch-up protection circuit is introduced as an intermediary component between the logic circuits and the external environment. This protection circuit monitors and controls current flow, detecting and preventing latch-up events before they can damage the integrated circuits, thus enabling high-density packaging while maintaining reliability.
2Reliability
If latch-up protection circuits are integrated within the chip, then device functionality is improved, but the area occupied by protection circuits reduces the area available for logic circuits
Solution Approach 1:
The device is segmented into two separate chips: the first chip is dedicated to logic circuits and the second chip to latch-up protection circuits. This segmentation allows each chip to be optimized for its specific function, maximizing the area available for logic circuits on the first chip while providing comprehensive protection functionality on the second chip.
Solution Approach 2:
Instead of adding protection circuits in the planar dimension (which would reduce logic circuit area), the solution moves to a three-dimensional architecture by stacking two separate chips. This vertical arrangement provides full latch-up protection functionality without consuming any additional lateral area on the logic circuit chip.
3Reliability
If separate chips are used for logic circuits and latch-up protection, then latch-up resistance is improved, but device complexity increases due to additional redistribution layers and interconnections
Solution Approach 1:
The second chip serving as a latch-up protection circuit is designed to be universally applicable to multiple first chips with different logic functions. The protection circuitry and redistribution layers are standardized, allowing the same second chip design to protect various logic circuit configurations, thereby reducing overall device complexity despite the multi-chip architecture.
Solution Approach 2:
The latch-up protection circuit, redistribution layers, and connection structures are merged into an integrated second chip assembly. This consolidation provides complete protection functionality in a single package, simplifying the overall device architecture and reducing the complexity of managing separate protection components for each logic circuit block.
Data Source
AI summary
An embodiment of the present application provides a method of manufacturing a semiconductor device including: forming a latch-up protection circuit; forming a first redistribution layer at a first side of the latch-up protection circuit, wherein the latch-up protection circuit is coupled a chip through the first redistribution layer; forming a hard block; forming a second redistribution layer at a first side of the hard block, wherein the hard block is coupled to the latch-up protection circuit through the second redistribution layer; and forming a first molding structure to surround the hard block, the second redistribution layer and the chip.