Latch Memory Circuit Write Balancing via Second-Node Boost
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The writing performance of latch circuits varies depending on whether the write data is at a low or high level, leading to poor balance and potential writing failures due to manufacturing variations, which reduces product yield.
Innovation Solution
A memory circuit with a latch circuit, a writing circuit, a command circuit, and a potential control circuit that detects the execution of writing and increases the potential of the second node before the termination of writing to ensure consistent data writing, using nMOS logic to reduce the number of control lines and improve balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional latch circuit writing is used, then the circuit structure is simple, but the writing performance varies depending on write data level leading to poor balance and potential writing failures
Solution Approach 1:
The potential control circuit pre-charges the second node to a high level before the writing operation begins. This preliminary action ensures that when writing occurs, the potential difference between nodes is optimized regardless of the write data level, preventing writing failures and balancing performance across different data levels.
Solution Approach 2:
The invention dynamically adjusts the potential of the second node based on the write data level. When write data is at a low level, the potential control circuit increases the second node's potential to maintain an adequate potential difference, thereby changing the electrical parameters to ensure consistent writing performance across different data levels.
2Area of stationary object
If nMOS logic is used in the writing circuit, then the number of control lines is reduced and area is minimized, but manufacturing variations may cause performance deviations
Solution Approach 1:
The command circuit detects whether writing is being executed and generates a command signal accordingly. This feedback mechanism ensures that the potential control circuit operates only when needed, maintaining optimal performance while minimizing unnecessary circuit activity that could be affected by manufacturing variations.
Solution Approach 2:
The potential control circuit pre-charges the second node before the writing operation based on the command signal. This preliminary action compensates for potential manufacturing variations by ensuring consistent initial conditions regardless of process deviations, thereby improving writing performance consistency.
3Reliability
If the potential of the second node is increased before writing termination, then writing performance balance is improved, but additional control circuitry is required
Solution Approach 1:
The potential control circuit serves multiple functions: it pre-charges the second node, maintains potential differences during writing, and operates only when commanded by the command circuit. This multi-functionality improves writing performance balance while minimizing the addition of dedicated control circuitry for each function.
Solution Approach 2:
The command circuit automatically detects writing execution and generates the appropriate command signal without external intervention. The potential control circuit then autonomously adjusts the second node's potential based on this command, reducing the need for additional complex control logic.
Data Source
AI summary
A memory circuit includes, a latch circuit that includes a first node, a second node, a first inverter having an input coupled to the first node and an output coupled to the second node, and a second inverter having an input coupled to the second node and an output coupled to the first node, a writing circuit that includes a first transistor coupled to the first node and a second transistor coupled to the second node and executes writing to the latch circuit using the first transistor and the second transistor, a command circuit detects the execution of the writing to the latch circuit and output a command signal to increase the potential of the second node before the termination of the writing of a low level to the first node, and a potential control circuit increases the potential of the second node based on the command signal.