Clock Polarity Control Circuit Using Latches and XOR Feedback
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Solution Overview
Problem
In wireless communication systems, particularly in advanced antenna systems and MIMO systems, the polarity of clock signals generated by frequency dividers is unknown, leading to potential phase correlation issues when multiple frequency dividers are used, which can cause operational problems.
Innovation Solution
A clock signal polarity controlling circuit is introduced, comprising two latches and an XOR circuit, where the data input of one latch is coupled to the output of a clock signal generator and the clock input is coupled to a reference clock signal, and the data input of the second latch is coupled to the output of the first latch with an inverted reference clock signal, allowing for the generation of a clock signal with controlled polarity through an XOR operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a latch based frequency divider is used to generate IQ clock signals, then the circuit complexity is reduced and generation is simplified, but the output signal polarity becomes unknown and cannot be controlled
Solution Approach 1:
The patent introduces a feedback mechanism where the output of the frequency divider is fed back through latches and XOR circuits to detect and control the polarity. The system samples the divided clock signal, compares it with a reference, and uses the comparison result to control inversion, thereby maintaining known polarity while keeping the frequency divider structure simple
Solution Approach 2:
The patent uses intermediary latches and XOR circuits as mediators between the frequency divider output and the final clock signal. These intermediaries detect the polarity state and conditionally invert the signal to ensure the desired polarity is achieved without modifying the core frequency divider circuit
2Adaptability or versatility
If multiple frequency dividers are used in the system, then the functionality is enhanced, but phase correlation between clock signals cannot be ensured due to unknown polarity
Solution Approach 1:
Each frequency divider incorporates a feedback control mechanism that detects its own output polarity and adjusts it accordingly. This ensures that all frequency dividers, regardless of their output polarity, produce clock signals with known and controllable polarity relationships, maintaining phase correlation across the system
Solution Approach 2:
The patent implements identical polarity control circuits in each frequency divider path, creating copies of the control mechanism. This ensures consistent polarity management across multiple dividers, allowing their outputs to be reliably combined or compared after frequency translation
Data Source
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AI summary
A clock signal polarity controlling circuit (100) comprises a first latch (110) comprising a clock input (clk), a data input (D) and an output (Q). The data input (D) is coupled to an output (121) of a clock signal generator (120), the clock input (clk) is coupled to a reference clock signal (Ref-clk). The clock signal polarity controlling circuit (100) further comprises a second latch (130) comprising a clock input (clk), a data input (D) and an output (Q). The data input (D) is coupled to the output of the first latch (110), the clock input (clk) is coupled to the reference clock signal (Ref-clk). The clock signal polarity controlling circuit (100) further comprises an XOR circuit (140) comprising a first and second inputs (141, 142) and an output (Out). The first and second inputs (141, 142) are coupled to the output of the second latch (130) and the output (121) of the clock signal generator (120) respectively, and a clock signal having a polarity controlled by the reference clock signal (Ref-clk) is generated at the output of the XOR circuit (140).