Latched Comparator Circuit for Wide Input Range and Low Power
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Solution Overview
Problem
Designing comparator circuits that meet specific operating specifications for various electronic devices and systems is challenging due to differences in voltage ranges, operating speed, power consumption, and comparator size.
Innovation Solution
The development of a latched comparator with a combination of NMOS and PMOS input transistors, allowing it to operate at a wider input common-mode range, higher speed, and lower power consumption, while maintaining uniform performance across different input signal values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional comparator circuits are designed to operate at high speed, then operating speed is improved, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by switching between different transistor configurations based on operational mode. During comparison operations, the circuit uses a first configuration optimized for speed, and during reset operations, it uses a second configuration optimized for low power consumption. This dynamic parameter switching resolves the contradiction between high-speed operation and low power consumption.
2Adaptability or versatility
If comparator circuits are designed to handle wider input voltage ranges, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamics by making the circuit configuration changeable over time through the reset mechanism. The comparator can dynamically switch between different operational states (comparison mode and reset mode) with different transistor configurations, allowing it to adapt to wider input voltage ranges without permanently increasing circuit complexity.
3Reliability
If comparator circuits use additional transistors to improve performance, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies periodic action by implementing a reset operation that periodically switches the transistor configurations. This periodic resetting ensures consistent performance by preparing the circuit in a known state before each comparison operation, improving reliability without requiring additional permanent circuit elements that would increase manufacturing cost.
Data Source
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AI summary
Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals.