Latched Cycle-by-Cycle Current Limit Indicator Circuit

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Solution Overview

Problem

Voltage regulators face inefficiencies in detecting and indicating cycle-by-cycle current limit events, leading to increased power consumption and processing time due to the need for multiple counts of overcurrent events.

Innovation Solution

A latched cycle-by-cycle current limit event indicator system that uses a latch signal to indicate overcurrent events over multiple clock cycles, utilizing flip-flops to delay the signal and reduce the need for repeated counting, thereby simplifying the reporting of overload information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional cycle-by-cycle current limit detection is used, then overcurrent events can be detected, but power consumption and processing time increase due to the need for multiple counts of overcurrent events

Engineering Contradiction:
Improveovercurrent event detection accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent applies preliminary action by implementing a latch circuit that is pre-configured to capture and hold overcurrent event signals. When an overcurrent event is detected, the latch circuit immediately latches the signal and maintains it for a predetermined number of clock cycles, eliminating the need for multiple counting operations. This preliminary setup of the latch mechanism reduces real-time processing requirements and associated power consumption while maintaining reliable detection accuracy.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional cycle-by-cycle current limit detection is used, then overcurrent events can be detected, but processing time increases due to the need for multiple counts of overcurrent events

Engineering Contradiction:
Improveovercurrent event detection accuracyVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The latch circuit is pre-configured with a predetermined latch duration based on a specific number of clock cycles. When an overcurrent event is detected, the circuit immediately latches the signal for the predetermined duration without requiring multiple counting operations, thereby reducing processing time while maintaining detection reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the time-consuming counting operation from the detection process by replacing it with a simple latch mechanism. The latch circuit directly captures and holds the overcurrent event signal for a predetermined period, eliminating the need for complex multiple-count verification and significantly reducing processing time while preserving detection accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If multiple counts of overcurrent events are required for indication, then reliable detection is achieved, but device complexity increases

Engineering Contradiction:
Improveovercurrent event detection accuracyVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the complex multiple-counting logic from the detection system by replacing it with a simple latch circuit. The latch mechanism directly captures overcurrent event signals and holds them for a predetermined number of clock cycles, eliminating the need for complex counting and verification logic while maintaining reliable detection accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The latch circuit creates a temporal copy of the overcurrent event signal by holding it for a predetermined duration. This copied signal provides sufficient information for reliable detection and indication without requiring the original complex multiple-counting process, thereby simplifying the overall device architecture.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20240297565A1Voltage regulator with latched cycle-by-cycle current limit indicator
Publication Date: 2024.09.05 RENESAS ELECTRONICS AMERICA INC
  • US20240297565A1 patent drawing
  • US20240297565A1 patent drawing
  • US20240297565A1 patent drawing

AI summary

Systems and methods for a cycle-by-cycle current limit event indicator is described. A circuit can include receiving a plurality of signals indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in a voltage regulator. The circuit can further include generating a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles. The latch signal can remain latched at high voltage for a number of clock cycles.