Latched MOS Circuit for Precise Piecewise Current Limiting
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Solution Overview
Problem
Existing current limiter circuits rely on uncertain variables like transistor threshold voltages and resistances, leading to imprecise current limiting functions, which are inadequate for many applications.
Innovation Solution
An electronic circuit using a latched MOS transistor pair with diode-connected MOS transistors to generate a piecewise linear current transfer function, incorporating current collecting circuits for maximizing and minimizing functions, and a class AB amplifier with differential architecture to enhance precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current limiter circuit is implemented using conventional transistors and resistors, then the circuit structure is simple, but the current limiting precision is poor due to uncertain variables like threshold voltages and resistances with accuracies of ±20%
Solution Approach 1:
The current transfer function is divided into multiple linear segments, each handled by a dedicated latched circuit module. This segmentation allows precise control over each segment's characteristics while maintaining overall precision through modular architecture.
Solution Approach 2:
The patent changes the operating parameters of MOS transistors by utilizing latched configurations where transistors switch between on and off states based on voltage comparisons. This parameter switching eliminates dependence on uncertain threshold voltages and resistance values, achieving precise current limiting.
2Reliability
If conventional current limiter circuits are used, then the device complexity is low, but the reliability of current limiting function is insufficient for many applications
Solution Approach 1:
The latched circuit modules incorporate feedback mechanisms where the output of one stage feeds back to control the switching of subsequent stages. This feedback ensures stable and reliable current limiting by continuously adjusting the transistor states based on the actual current conditions.
Solution Approach 2:
The circuit performs preliminary voltage comparisons and current regulation through the latched MOS transistor configuration before the actual current limiting action occurs. This preliminary action ensures that the current limiting function is activated at the precise moment needed, improving reliability.
3Manufacturing precision
If piecewise linear current transfer function is implemented with multiple latched circuit modules, then the current precision is improved, but the device complexity increases
Solution Approach 1:
Each latched circuit module is designed as a universal building block that can be replicated and cascaded to create different piecewise linear transfer functions. The same module structure serves multiple purposes by adjusting the reference voltages and transistor dimensions, reducing overall system complexity.
Solution Approach 2:
The latched circuit modules are nested in a cascaded configuration where the output of one module serves as the input to the next. This nesting allows the complex piecewise linear function to be built from simpler identical modules, making the overall complexity manageable through modular design.
Data Source
AI summary
A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.