Latching Predecoder Circuitry for Clocked Memory Word Line Selection
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Solution Overview
Problem
Existing clocked memories face challenges in efficiently selecting word lines due to unreliable timing in initiating the word line selection process, particularly in combining address response and decoded output, often relying on delayed clock signals that prolong the detection time unnecessarily.
Innovation Solution
The implementation of predecoder circuitry that provides latched predecoded signals to word line driver logic, allowing immediate resolution of address combinations in response to a clock signal early in the clock cycle, thereby reducing the need for the address combinations to be latched throughout the entire cycle and enabling efficient word line selection and preparation for the next selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delayed clock signal is used to control word line selection, then the address signal has sufficient time to be fully developed and detected reliably, but the overall detection time is unnecessarily extended
Solution Approach 1:
The predecoder circuitry performs preliminary decoding of address signals in advance, generating predecoded signals before the main decoding stage. This preliminary action allows the main decoder to start its operation earlier in the clock cycle, reducing the overall detection time while maintaining reliable signal development through the staged decoding approach.
Solution Approach 2:
The decoding process is segmented into two stages: a predecoder stage that performs initial address decoding, and a main decoder stage that completes the word line selection. This segmentation allows each stage to operate independently with optimized timing, enabling the predecoder to prepare signals early while the main decoder finalizes the selection, thus reducing total detection time without compromising reliability.
2Reliability
If the address combinations are latched throughout the entire clock cycle, then the word line selection can be performed reliably, but the circuit cannot prepare for the next word line selection efficiently
Solution Approach 1:
The predecoder circuitry performs preliminary decoding of address signals in advance, generating predecoded signals before the main decoding stage. This preliminary action allows the main decoder to start its operation earlier in the clock cycle, reducing the overall detection time while maintaining reliable signal development through the staged decoding approach.
Solution Approach 2:
The decoding process is segmented into two stages: a predecoder stage that performs initial address decoding, and a main decoder stage that completes the word line selection. This segmentation allows each stage to operate independently with optimized timing, enabling the predecoder to prepare signals early while the main decoder finalizes the selection, thus reducing total detection time without compromising reliability.
Data Source
AI summary
A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.