Late Read Buffer Assignment in Data Storage Systems

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Solution Overview

Problem

Data storage systems face performance bottlenecks and inefficiencies due to suboptimal data transfer speeds and buffer management, particularly in systems using NAND flash memory, where data input and output processes are inefficient, leading to increased processing time and latency.

Innovation Solution

A data storage system that employs a buffer module to reactively assign a data read buffer destination only after the data arrives, utilizing real-time and predictive assessments of system conditions to optimize data flow and reduce latency by intelligently managing data between on-chip and off-chip buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data read buffer destination is assigned before data arrives, then buffer management is simplified, but data transfer speed decreases and read latency increases

Engineering Contradiction:
Improvebuffer management complexityVSAvoiddata transfer speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The system dynamically assigns read buffer destinations after data arrives in the cache, rather than using static pre-assignment. The buffer module evaluates current system conditions and selectively places data in optimal buffers (first memory buffer for single hosts, second memory buffer for multiple hosts) based on real-time assessment, thereby optimizing data transfer speed while maintaining manageable complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The buffer module autonomously evaluates system conditions and makes intelligent decisions about buffer assignment without requiring complex external control. It self-determines the optimal buffer destination by assessing current system state, thereby improving data transfer speed while keeping the control mechanism relatively simple

Inventive Principle:
Principle #25Self-service

2Productivity

If data read buffer destination is assigned before data arrives, then processing workflow is streamlined, but read latency increases

Engineering Contradiction:
Improveprocessing workflow efficiencyVSAvoidread latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system uses dynamic buffer assignment after data arrival to optimize read latency. By evaluating real-time system conditions at the moment data is available in cache, the system can immediately direct data to the most appropriate buffer, minimizing waiting time and reducing read latency while maintaining efficient processing workflows

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary evaluation of system conditions and buffer availability at the moment data arrives in cache, before actual data transfer begins. This allows the buffer module to make optimal buffer selection decisions quickly, reducing read latency while maintaining streamlined processing

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple buffers are evaluated after data arrival, then data is positioned in optimal locations, but buffer management complexity increases

Engineering Contradiction:
Improvedata flow efficiencyVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer module applies different buffer selection criteria based on local system conditions. It evaluates whether to place data in the first memory buffer or second memory buffer based on specific local factors such as current buffer availability and host request patterns, thereby optimizing data flow efficiency while keeping the management logic relatively simple through localized decision-making

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically evaluates multiple buffers after data arrival and selects the optimal destination based on current system state. This dynamic approach optimizes data flow efficiency by positioning data in the most appropriate buffer at the moment of arrival, while the evaluation process remains manageable through structured condition assessment

Inventive Principle:
Principle #15Dynamics

4Loss of time

If reactive buffer assignment after data arrival is used, then read latency is reduced, but processing complexity increases

Engineering Contradiction:
Improveread latencyVSAvoidprocessing complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The buffer module autonomously performs reactive buffer assignment by evaluating system conditions and making intelligent decisions without requiring complex external control mechanisms. It self-determines the optimal buffer destination based on current system state, thereby reducing read latency while keeping processing complexity manageable through self-contained decision logic

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11294572B2Data storage system with late read buffer assignment after arrival of data in cache
Publication Date: 2022.04.05 SEAGATE TECH LLC
  • US11294572B2 patent drawing
  • US11294572B2 patent drawing
  • US11294572B2 patent drawing

AI summary

A data storage system may have a number of data storage devices that each have a non-volatile memory connected to different first and second memory buffers. A data storage device can consist of a non-volatile memory where a data sector is stored. A network controller can consist of a buffer module connected to a first memory buffer and a second memory buffer that receives a data read request from the host for the data sector and evaluates the first and second memory buffers as a destination for the data sector after the data sector arrives at the buffer module. The buffer module may choose the first memory buffer and store the data sector in the first memory buffer prior to providing the data sector to the host to satisfy the data read request from the first memory buffer.