Late In-Situ Doped SiGe Junctions for PMOS Devices
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Solution Overview
Problem
The 28SLP process lacks embedded source/drain stressors like SiGe in PMOS devices, leading to lower hole mobility and insufficient performance for high-speed operation with low power consumption.
Innovation Solution
Incorporating an in-situ-doped late SiGe process flow into the HKMG CMOS device formation, involving the formation of high-k metal gate stacks, nitride and oxide spacers, and epitaxial growth of SiGe in cavities, with boron doping and subsequent silicide formation to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded SiGe source/drain regions are incorporated into PMOS devices, then hole mobility and drive current are improved, but process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies preliminary action by forming nitride and oxide spacers before the SiGe epitaxial growth to define the source/drain regions. The spacers are formed in advance to protect the gate during subsequent implantation and epitaxy steps, and to precisely define where the SiGe will grow. This preliminary structuring enables the complex SiGe integration without requiring additional alignment steps during the critical epitaxial growth phase.
Solution Approach 2:
The patent segments the source/drain formation process into distinct stages: first forming nitride spacers, then oxide spacers, followed by selective SiGe epitaxial growth in the defined regions. This segmentation allows each layer and step to be optimized independently - the nitride provides mechanical support and etch selectivity, the oxide provides spacer functionality and protection, and the SiGe grows only in the intended locations. This modular approach manages the overall process complexity.
2Manufacturing precision
If late in-situ doped SiGe is formed after all implants, then doping precision and electrical performance are improved, but process steps and manufacturing complexity increase
Solution Approach 1:
The patent merges the doping step with the SiGe epitaxial growth step by using in-situ doped SiGe. The dopants (boron for PMOS) are introduced during the epitaxial growth process itself rather than requiring a separate implantation step. This combining achieves precise doping profiles because the dopants are incorporated uniformly during growth, and it reduces the total number of process steps by eliminating a dedicated doping step that would require additional masking and alignment.
Solution Approach 2:
The patent changes the timing parameter of dopant introduction from post-growth implantation to during-growth in-situ doping. This parameter change allows the dopants to be incorporated into the SiGe lattice during the epitaxial growth process, achieving better doping precision and uniformity. The in-situ doping approach also changes the concentration profile control from ion implantation parameters to epitaxial growth parameters, enabling more precise control over the final electrical properties.
3Reliability
If multiple spacer layers (nitride and oxide) are formed, then device performance and strain engineering are improved, but manufacturing cost and process time increase
Solution Approach 1:
The patent applies multi-functionality to the nitride and oxide spacer layers. The nitride spacers serve multiple functions: they provide mechanical support during processing, offer etch selectivity for defining the source/drain regions, and contribute to strain engineering in the channel. The oxide spacers similarly provide spacer functionality, protection during subsequent steps, and additional strain control. By making each layer multi-functional, the patent justifies the additional layers through their multiple benefits rather than requiring separate dedicated layers for each function, thereby improving throughput.
Solution Approach 2:
The patent uses composite material structures with nitride and oxide spacers formed in sequence. The combination of these two different materials provides complementary properties: nitride offers high mechanical strength and good etch selectivity, while oxide provides good spacer characteristics and additional protection. This composite spacer structure enables precise definition of the SiGe source/drain regions while providing the necessary mechanical and chemical protection during processing, achieving both high device performance and reasonable manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves yield, reduces contact resistance, increases carrier mobility and drive current, and lowers manufacturing costs while maintaining low power consumption, enhancing PMOS device performance.
Implementation Method 1
forming a nitride liner and oxide spacers on each side of each of the first and second HKMG gate stacks
Implementation Method 2
performing halo/extension implants at each side of each of the first and second HKMG gate stacks
Implementation Method 3
forming a cavity by wet etching with tetramethylammonium hydroxide (TMAH)
Implementation Method 4
epitaxially growing SiGe in the cavity
Implementation Method 5
annealing to activate implanted dopants after forming the oxide hardmask
Data Source
AI summary
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.