Transition-Detecting Sequential Circuit for Late Timing Errors
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Solution Overview
Problem
Conventional microprocessor clock frequency is unnecessarily limited by worst-case operating parameters, leading to high clock energy consumption and susceptibility to datapath metastability issues due to the use of additional latch and error-detection circuitry in flip-flops.
Innovation Solution
Implementing a transition detector with a time borrowing latch (TDTB) in sequential circuits to detect and correct late transitions, reducing clock frequency guardbands and eliminating datapath metastability, while maintaining error-detection features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error-detection circuitry with latch and XOR gate is used to detect late transitions, then error detection capability is improved, but clock energy consumption increases and device complexity increases
Solution Approach 1:
The patent extracts the error detection function from the traditional latch-XOR gate structure and implements it using the inherent behavior of a single edge-triggered flip-flop. The flip-flop naturally captures late transitions without requiring additional error-detection circuitry, thereby eliminating the extra latch and XOR gate that consume clock energy.
Solution Approach 2:
The single edge-triggered flip-flop serves multiple functions: it acts as both the sequential element for data storage and the error detection mechanism. By using the flip-flop's natural transparent phase behavior during clock high period, it automatically detects late transitions without requiring separate dedicated error detection components.
2Reliability
If additional latch and error-detection circuitry are employed to account for dynamic extremes, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex multi-component error detection structure (latch, XOR gate, metastability detector) and replaces it with the natural behavior of a single edge-triggered flip-flop. The flip-flop's transparent phase inherently provides error detection capability without requiring additional circuit elements.
Solution Approach 2:
The edge-triggered flip-flop performs error detection on its own without requiring external error-detection circuitry. During its transparent phase when the clock is high, the flip-flop automatically captures any late transitions that occur, making the error detection function self-contained within the sequential element itself.
3Productivity
If clock frequency is increased beyond worst-case parameters, then productivity is improved, but timing errors may occur due to dynamic variations
Solution Approach 1:
The patent implements a timing error detection mechanism where the edge-triggered flip-flop monitors for late transitions during its transparent phase. When a timing error occurs (late transition during transparent phase), an error signal is generated that can trigger corrective actions such as inserting pipeline bubbles or adjusting timing, thereby maintaining reliability at higher clock frequencies.
Data Source
AI summary
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.