Latency-Aware Memory Modeling for Faster SoC Emulation
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Solution Overview
Problem
Existing circuit design verification methods for complex integrated circuits, such as SoC designs, face inefficiencies in memory modeling due to slow software-based simulations and emulation/prototyping systems that incur significant performance penalties from cache misses and complex cache lookup structures, especially when modeling large memories.
Innovation Solution
A memory compiler is configured to model latency by tailoring memory modeling interfaces to specific protocols and implementation options, using system calls and latency-aware structures like pipelines and FIFOs to optimize emulation clock speeds and reduce model stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based simulation is used for verifying large complex designs, then verification can be performed, but execution speed becomes too slow due to cache misses and memory swapping
Solution Approach 1:
The patent introduces a hybrid hardware-software emulation system where frequently accessed memory data is stored in hardware memory resources on the emulator, acting as an intermediary between the software simulator and the actual memory. This mediator approach allows the system to maintain verification correctness while dramatically improving execution speed by avoiding cache misses and memory swapping for frequently accessed data.
Solution Approach 2:
The patent segments the memory system into multiple levels: hardware memory resources on the emulator for frequently accessed data, and software-based memory for less frequently accessed data. This segmentation allows the system to optimize for speed where needed while maintaining completeness, resolving the contradiction between verification reliability and execution speed.
2Quantity of substance
If memory is placed on board or system board in emulator, then larger memory capacity is available, but access speed decreases due to larger distance from access point
Solution Approach 1:
The patent applies local quality by placing different types of memory resources in different locations within the emulator architecture. High-speed memory resources are placed locally close to the logic being emulated, while larger capacity memory resources are placed on boards farther away. This allows the system to provide both large memory capacity and fast access speed by using the appropriate memory resource depending on the access pattern.
3Quantity of substance
If cache-based implementation is used for memory, then medium to large memories can be implemented, but performance degrades due to cache misses requiring page fetch from software
Solution Approach 1:
The patent uses preliminary action by pre-loading frequently accessed memory pages into the hardware cache memory before they are actually needed during emulation. The system monitors access patterns and proactively fetches data into the hardware memory resources, so that when emulation needs this data, it is already available in fast hardware memory, avoiding page fetches from software and maintaining high emulation throughput.
4Quantity of substance
If complex cache lookup logic structures are used, then larger memory can be accessed, but emulation clock speed decreases due to multiple memory accesses in series
Solution Approach 1:
The patent segments the cache lookup logic into multiple independent parallel lookup structures, each handling a portion of the memory space. Instead of using a single complex sequential lookup that requires multiple memory accesses, the system uses multiple simpler parallel lookup tables that can be queried simultaneously, reducing the critical path and enabling higher emulation clock speeds while still supporting large memory capacities.
Data Source
AI summary
Systems and methods for emulate or prototyping of hardware, such as memory, are disclosed. A memory compiler may receive information, such as system calls, indicative of one or more aspects of latency. Responsive to the information, the memory compiler may create infrastructure, such as pipelines and FIFOs, based on the aspects of latency, for emulation or prototyping of the hardware. Using the created infrastructure may improve emulation compile speed, such as by creating a pipeline-based cache structure, and may improve emulation runtime speed, such as by utilizing earlier unused model clocks to fetch data from host sooner.