Latency-Based Instruction Reservation Clustering in Processor Scheduler
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Solution Overview
Problem
Conventional scheduler circuits in processors face challenges in increasing instruction window size to enhance performance while maintaining low scheduling latency, as larger window sizes increase complexity and latency due to the need for more scheduling path connections.
Innovation Solution
Implementing a latency-based clustered scheduler circuit with multiple latency-based reservation circuits, each assigned a specific producer instruction cycle latency, allowing consumer instructions to be clustered and scheduled accordingly, reducing the number of scheduling path connections and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the instruction window size is increased to enhance processor performance, then the number of reservation entries is increased, but the scheduling path connections and circuit complexity increase, leading to increased scheduling latency
Solution Approach 1:
The scheduler circuit is divided into multiple independent latency-based reservation circuits (e.g., 1-cycle latency circuit, 2-cycle latency circuit, 3-cycle latency circuit). Each circuit handles instructions with specific latency requirements separately, avoiding the need for a single large reservation circuit with complex interconnections. This segmentation reduces the scheduling path connections within each subset while maintaining the overall instruction window size.
Solution Approach 2:
A wake-up signal mechanism is introduced as an intermediary to coordinate between different latency-based reservation circuits. When a producer instruction completes execution, it generates a wake-up signal that triggers the readiness of consumer instructions in the appropriate latency circuit. This intermediary mechanism enables efficient scheduling across multiple circuits without requiring complex direct connections between all reservation entries.
2Productivity
If the instruction window size is increased to enhance processor performance, then the number of reservation entries is increased, but the scheduling latency increases, preventing consumer instructions from being issued in back-to-back clock cycles
Solution Approach 1:
By segmenting the reservation circuit into latency-based subsets, each subset has a dedicated, optimized scheduling path with minimal connections. This ensures that consumer instructions in each latency group can be scheduled with low latency, maintaining the capability to issue instructions in back-to-back clock cycles despite the overall increased instruction window size.
Solution Approach 2:
The system changes the organizational parameter of the reservation circuit from a flat structure to a hierarchical latency-based structure. Instructions are grouped by their latency parameters (1-cycle, 2-cycle, 3-cycle), and each group is scheduled independently. This parameter change optimizes the scheduling path length for each group, reducing overall scheduling latency while maintaining large instruction window size.
Data Source
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Figure 2A
Figure 2B-1~2B-2
AI summary
Latency-based instruction reservation clustering in a scheduler circuit in a processor is disclosed. The scheduler circuit includes a plurality of latency-based reservation circuits each having an assigned producer instruction cycle latency. Producer instructions with the same cycle latency can be clustered in the same latency-based reservation circuit. Thus, the number of reservation entries is distributed among the plurality of latency-based reservation circuits to avoid or reduce an increase in the number of scheduling path connections and complexity in each reservation circuit to avoid or reduce an increase in scheduling latency. The scheduling path connections are reduced for a given number of reservation entries over a non-clustered pick circuit, because signals (e.g., wake-up signals, pick-up signals) used for scheduling instructions in each latency-based reservation circuit do not have to have the same clock cycle latency so as to not impact performance.