Latency-Compensated PLL for Stable High-Speed Clock Control
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Solution Overview
Problem
Phase-locked loop (PLL) circuits face instability due to loop latency, which degrades their performance and fails to meet stringent frequency requirements and low clock skew distributions, especially at high speeds.
Innovation Solution
The introduction of a loop latency compensated PLL design that includes an ADC, phase detector, loop filter, and VCO, where the loop filter generates a latency compensated phase error by reserving the sign-bit of the estimated phase error or uses a latency compensator to provide phase correction, and a PLL capable of switching between high speed and low speed operating modes to adjust latency based on application needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL circuits are used, then the circuit structure is simple, but loop latency causes instability and performance degradation
Solution Approach 1:
The patent applies preliminary action by predicting the phase error that will occur after loop latency using the current phase error and a predicted phase error coefficient. This prediction is performed in advance before the actual phase error is measured, allowing the system to compensate for the delayed feedback without waiting for the latency to manifest. The predicted phase error is then used to generate the control signal for the VCO, effectively counteracting the instability caused by loop latency.
2Productivity
If high clock rates are used, then productivity increases, but clock skew and frequency requirements become more stringent
Solution Approach 1:
The patent employs feedback by continuously monitoring the phase error between the reference clock and the VCO output, and using this information to adjust the VCO frequency. The feedback mechanism includes a phase detector that measures phase error, a predicted phase error coefficient generator that calculates the predicted phase error coefficient based on the phase error, and a predicted phase error generator that uses both the current phase error and the predicted coefficient to generate the control signal. This closed-loop feedback system enables precise clock skew control even at high clock rates.
3Reliability
If loop latency is not compensated, then device complexity is low, but performance and frequency requirements are not met
Solution Approach 1:
The patent introduces an intermediary element - the predicted phase error coefficient - that mediates between the current phase error measurement and the required control signal for VCO adjustment. This coefficient acts as a bridge that translates the phase error information into a predicted future phase error, which then becomes the basis for generating the control signal. The intermediary allows the system to account for loop latency without requiring direct measurement of the delayed phase error.
Data Source
AI summary
A loop latency compensated phase-locked loop (PLL). The loop latency compensated PLL comprises an ADC, a phase detector, a loop filter and a VCO. The ADC receives an analog input signal and an output clock to generate a digital signal. The phase detector receives the digital signal to generate an estimated phase error. The loop filter receives the estimated phase error to generate a latency compensated phase error output signal with a phase assigned by a sign-bit of the received estimated phase error. The VCO generates the output clock in response to the latency compensated phase error output signal and feeds the output clock back to the ADC.