Latency Control Circuit for CAS Timing at High Data Rates
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Solution Overview
Problem
Existing latency control circuits in semiconductor devices face challenges in maintaining total delay time below the product of CAS latency and clock cycle as data rates increase and clock cycles decrease, especially under low power supply conditions, making it difficult to compensate for command decoder, clock buffer, and serializer delays.
Innovation Solution
A latency control circuit that includes a clock delay, deviation information generator, clock selector, command signal processor, and latency shifter to compensate for command decoder, clock buffer, and serializer delays by generating serial delay signals, deviation information, and variable delay duplication signals, allowing for flexible clock selection and delay adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased and clock cycle is decreased, then productivity is improved, but total delay time cannot be maintained below CAS latency × clock cycle
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay compensation values in a delay compensation value storage unit before they are needed. The system predicts future delay requirements based on operating conditions (data rate, supply voltage) and prepares compensation values in advance, allowing the latency control circuit to quickly adjust without adding critical path delay during actual operation.
Solution Approach 2:
The patent implements dynamics by making the latency control circuit adjustable and adaptive to different operating conditions. The system dynamically selects different delay compensation values based on actual data rates and supply voltages, and the latency control circuit can be reconfigured during operation to maintain optimal performance across varying conditions rather than being fixed for a single operating point.
2Use of energy by moving object
If supply voltage is decreased for power saving, then energy consumption is reduced, but delay compensation becomes more difficult
Solution Approach 1:
The system pre-calculates delay compensation values for various supply voltage conditions and stores them in advance. When supply voltage changes, the system retrieves the pre-computed compensation value corresponding to the new voltage level, avoiding the need to perform complex delay measurements and adjustments in real-time under low-voltage conditions where timing is critical.
Solution Approach 2:
The patent applies parameter changes by adjusting delay compensation based on supply voltage levels. The system monitors supply voltage and selects appropriate delay compensation values from stored data that are optimized for specific voltage ranges, allowing the circuit to maintain proper timing even when operating voltage varies to balance power consumption and performance.
3Device complexity
If fixed latency control circuit is used, then device complexity is reduced, but adaptability to different data rates and CAS latencies is limited
Solution Approach 1:
The patent implements dynamics by creating a latency control circuit that can be reconfigured during operation. The system uses a latency control signal generated by combining the read command with delay compensation to dynamically adjust the timing of read operations. This allows the same hardware circuit to adapt to different data rates and CAS latency requirements without requiring multiple fixed circuits, achieving versatility through controlled reconfiguration rather than hardware multiplication.
Data Source
AI summary
A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.