Latency Control Circuit Using Phase-Shifted Clocks for DDR Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DDR synchronous memory devices face challenges in high-speed operations due to difficulties in effectively transmitting or receiving data within one clock period using conventional data access schemes, leading to inefficiencies in bandwidth and synchronization with external clocks.
Innovation Solution
A latency control device and semiconductor device are designed to include delay controllers, a selection circuit, and a DLL circuit, which generate internal clocks with different phases to control latency signals, allowing for the extraction of rising or falling edges in response to test signals, thereby testing and optimizing latency operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DDR synchronous memory device uses conventional data access scheme, then device complexity is reduced, but bandwidth and operational speed cannot be improved
Solution Approach 1:
The patent segments the data access scheme into separate write path and read path configurations. The write path includes a write buffer and write data latch, while the read path includes a read buffer and read data latch. This segmentation allows independent optimization of each path for DDR operations, enabling doubled bandwidth through separate write and read configurations without overwhelming complexity.
Solution Approach 2:
The patent implements dynamic path selection through control signals that can switch between different data access configurations. The write buffer and read buffer can be selectively activated based on operation mode, allowing the system to dynamically adapt between single data rate and double data rate operations, thereby improving bandwidth while maintaining manageable complexity through controlled flexibility.
2Speed
If DDR synchronous memory device transmits two pieces of data within one clock period, then operational speed increases, but difficulty in synchronizing with external clock increases
Solution Approach 1:
The patent introduces DLL (Delay Locked Loop) circuits as intermediary components that generate phase-shifted clock signals. These DLL-generated clocks serve as intermediaries between the external clock and the internal data latching operations, making it easier to synchronize dual data transmissions with the external clock by providing ready-made phase references at 0°, 90°, 180°, and 270°.
Solution Approach 2:
The patent utilizes periodic clock phases generated by the DLL circuit to handle the two data transmissions within one external clock period. By dividing the external clock period into four equal phases and using appropriate phases for write and read operations, the system achieves doubled operational speed while maintaining synchronization through regular, predictable timing intervals.
3Measurement precision
If test signal activates to test latency operation, then measurement precision improves, but device operation is interrupted
Solution Approach 1:
The patent extracts the latency measurement function into a separate, dedicated test mode that can be independently activated. When a test signal is detected, the system transitions to test mode where latency measurement circuits are activated and normal data processing is suspended. This separation allows precise latency measurement without permanently affecting device operation, as the system can return to normal operation after testing.
Solution Approach 2:
The patent implements preliminary detection of test signals that activate the measurement mode before actual latency measurement begins. This preliminary action allows the system to prepare measurement circuits and suspend normal operations in advance, ensuring accurate measurements are taken during a controlled window, then恢复正常 operations afterward, minimizing overall disruption.
Data Source
AI summary
A latency control device and a semiconductor device including the same may be provided. The latency control device may include a first delay controller configured to delay a command signal based on a first internal clock having a first phase and a control signal. The latency control device may include a second delay controller configured to delay the command signal based on a second internal clock having a second phase different from the first phase and a test control signal. The latency control device may include a selection circuit configured to select any one of an output signal of the first delay controller and an output signal of the second delay controller based on a selection signal, and output a latency signal. The latency control device may include a test controller configured to generate the test control signal based on the control signal and a test signal.