Latency Information Control via Logical Block Addressing
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Solution Overview
Problem
Current storage systems face challenges in minimizing latency, particularly in solid state storage devices, as existing mechanisms for monitoring latency require frequent use of performance-sensitive commands that impact drive performance and bandwidth, and there is a need for cost-effective methods to enhance computer operations without relying on special purpose commands.
Innovation Solution
A method and apparatus that control latency information through logical block addressing by receiving computer commands, performing read operations, populating metadata frames with latency data, and modifying the system to operate at a different latency level, allowing for transparent data transmission without using special commands, utilizing existing metadata fields in SAS data frames to convey logical block address latency information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional log sense commands are issued to monitor latency and retrieve caching statistics, then latency information can be obtained, but host system performance deteriorates due to bandwidth consumption and performance-sensitive command execution
Solution Approach 1:
The patent introduces an intermediary mechanism where the storage device itself generates and transmits latency information through existing data transfer protocols. Instead of the host issuing specialized monitoring commands, the storage device autonomously creates latency data structures that are transmitted alongside normal data transfers, eliminating the need for separate performance-sensitive monitoring commands from the host.
Solution Approach 2:
The storage device performs self-monitoring of latency by internally tracking timing information during data transfers. The device autonomously generates latency information without requiring host intervention or specialized commands, effectively serving its own monitoring needs while transparently providing this information to the host through standard data paths.
2Measurement precision
If frequent latency analysis commands are issued to retrieve performance data, then latency can be monitored, but drive performance deteriorates due to command frequency impacting bandwidth and processing resources
Solution Approach 1:
The patent merges latency monitoring functionality with existing data transfer operations. Latency information is combined with normal data streams rather than being separated into distinct monitoring commands. This integration allows latency monitoring to occur as a byproduct of regular data transfers, eliminating the need for additional command overhead and preserving drive performance.
Solution Approach 2:
The latency monitoring mechanism operates continuously during normal data transfer without requiring intermittent command issuance. By embedding monitoring within the data transfer process itself, the system maintains continuous latency awareness while avoiding the startup and processing overhead of separate monitoring commands, thus sustaining drive performance.
3Measurement precision
If special purpose commands are used to retrieve latency information, then accurate latency data can be obtained, but system complexity increases and cost-effectiveness decreases
Solution Approach 1:
The patent makes the existing data transfer protocol universal by enabling it to carry both normal data and latency information simultaneously. The same protocol that handles regular data transfers also transports monitoring data, eliminating the need for separate specialized commands. This multi-functionality reduces command mechanism complexity while maintaining measurement precision.
Solution Approach 2:
The patent creates a copy of latency information within the data transfer structure itself. By embedding latency data alongside normal data streams, the system creates a parallel information copy that can be extracted by the host without requiring separate command sequences. This copying approach simplifies the command mechanism while preserving accurate latency measurement capability.
Data Source
AI summary
A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.