Latency Control Device for Semiconductor Screen Test Throughput
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Solution Overview
Problem
Conventional latency control circuits in semiconductor devices are limited by their synchronization with a clock signal, restricting minimum and maximum latency delay amounts and thereby limiting screen-test throughput.
Innovation Solution
A latency control device and semiconductor device that include a latency unit for normal latency signals synchronized with a clock, a self-latency unit for asynchronous operation, and a selection unit to choose between normal and self-latency signals, allowing for adaptive latency control by setting a code corresponding to a desired delay amount.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional latency control circuit operates in synchronization with a clock signal, then the circuit can maintain stable timing control, but the latency delay amount is limited to a minimum of one clock period and a maximum of (clock period)×(number of flip-flops)
Solution Approach 1:
The latency control circuit is divided into two independent paths: a synchronous latency control path using flip-flops for stable timing, and an asynchronous latency control path using a counter for extended delay range. The selection unit chooses between these two paths based on the required latency, allowing the system to achieve both stability and adaptability.
Solution Approach 2:
The invention combines two different latency control mechanisms (synchronous flip-flop-based control and asynchronous counter-based control) into a unified latency control device. This composite approach allows the system to leverage the stability of synchronous control while extending the delay range through asynchronous control, resolving the contradiction between reliability and adaptability.
2Device complexity
If the maximum latency delay amount is denoted by (clock period)×(number of flip-flops), then the circuit structure remains simple, but the screen test throughput is limited
Solution Approach 1:
The invention introduces a dynamic latency control mechanism where the latency period can be adjusted beyond fixed clock period multiples. The counter unit allows the latency to be dynamically set to any value within the extended range, enabling the system to adapt to different screen test requirements and improve throughput without significantly increasing circuit complexity.
Solution Approach 2:
The invention changes the latency parameter from being constrained to discrete clock period multiples to being adjustable within a continuous range. By using a counter unit with load and enable signals, the system can set the latency period to any desired value, thereby improving screen test throughput while maintaining reasonable circuit complexity.
3Adaptability or versatility
If a latency control circuit uses serial shift operation through flip-flops to process contiguous command signals, then the circuit can handle multiple signals, but the processing speed is limited by the clock period
Solution Approach 1:
The counter unit is pre-loaded with a desired latency value before processing command signals. This preliminary action allows the counter to generate the appropriate delay without being constrained by clock period increments during signal processing, thereby improving the speed at which contiguous command signals can be processed while maintaining the ability to handle multiple signals.
Data Source
AI summary
A latency control device and a semiconductor device including the same are disclosed. The latency control device includes: a code setting unit configured to output a plurality of coding signals by setting a code value having a specific delay amount in response to a code signal; a latch unit configured to latch a command signal for a predetermined time; a period control unit configured to control a delay amount of a period signal in response to an output signal of the latch unit; a selection unit configured to output an oscillation signal synchronized with the clock signal in response to the selection signal, or synchronize the oscillation signal with an output signal of the period control unit; a register unit configured to output a plurality of period signals by dividing the oscillation signal; and a comparator configured to compare the plurality of coding signals with the plurality of period signals so as to output the self-latency signal.