Latency Control Circuit for Precise On-Die Termination Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor apparatuses face challenges in compensating for signal processing delays and matching impedance for termination operations, particularly in receiving external termination signals and clock signals, which affects the latency and efficiency of on-die termination processes.
Innovation Solution
A latency control circuit and semiconductor apparatus that utilize a delay-locked loop to generate delay-locked termination and clock signals, with separate signal paths for controlling latency using divided clock signals and their inverses, allowing for precise latency adjustment and signal combination to generate a latency-controlled termination signal for effective impedance matching at input/output pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single signal path is used for termination signal processing, then the device complexity is reduced, but the latency control precision deteriorates
Solution Approach 1:
The patent divides the termination signal processing into two separate signal paths: a first signal path that processes the delay-locked termination signal using a first divided clock signal, and a second signal path that processes it using a second divided clock signal. This segmentation allows independent latency control in each path, achieving precise latency adjustment while maintaining manageable complexity through modular design.
2Manufacturing precision
If latency control is performed without separate signal paths, then the device complexity is reduced, but the latency adjustment precision deteriorates
Solution Approach 1:
The patent employs dynamic latency control by using multiple divided clock signals with different phases to adjust the latency of the termination signal. The latency can be dynamically adjusted by selecting different clock signals and combining them through logical operations, enabling flexible and precise latency control without requiring a completely static circuit design.
Solution Approach 2:
The patent introduces a temporal dimension to latency control by using clock signals with different phases and divisions. Instead of adjusting latency through a single dimensional parameter, the invention uses multiple time dimensions (different clock phases and divisions) to achieve precise latency adjustment, effectively adding another degree of freedom to the control mechanism.
3Measurement precision
If multiple divided clock signals are used for latency control, then the latency control precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges the outputs of multiple signal paths that use different divided clock signals through a combination unit. By logically combining the results from parallel processing paths, the system achieves precise latency control using multiple clock signals while reducing the overall complexity compared to having completely separate processing chains for each clock signal.
Data Source
AI summary
A latency control circuit may include a first latency control section configured to control a latency of a delay-locked termination signal according to a first divided clock signal, and generate a first preliminary signal, and a second latency control section configured to control the latency of the delay-locked termination signal according to a first divided clock bar signal which is generated by inverting the first divided clock signal, and generate a second preliminary signal. The latency control circuit may also include a signal combination unit configured to shift the first preliminary signal and the second preliminary signal by latency values set differently from each other, according to the first divided clock signal, and generate a first combined signal and a second combined signal, and a signal generation unit configured to generate a latency-controlled termination signal in response to the first combined signal and the second combined signal.