Latency-Controlled IDE Circuit With Precomputed AES Data
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Solution Overview
Problem
The CXL® protocol is highly sensitive to latency, and existing IDE algorithms like AES-GCM incur a latency penalty due to the need for buffer storage and additional memory, which increases area and power consumption.
Innovation Solution
A latency-controlled cryptographic circuit that pre-calculates AES data in advance, eliminating the need for additional buffers or SRAM by synchronizing input data arrival with AES data readiness, achieving zero or low latency through an XOR operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer storage and additional memory are used for IDE algorithms like AES-GCM, then data integrity and encryption can be achieved, but latency increases and area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating AES data in advance before it is needed. The system performs encryption/decryption operations ahead of time so that when data arrives, the cryptographic processing is already ready, eliminating the need for buffering and reducing latency while maintaining data integrity
2Reliability
If buffer storage and additional memory are used for IDE algorithms like AES-GCM, then data integrity and encryption can be achieved, but area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the need for buffer storage and additional memory by implementing a streamlined cryptographic circuit that performs AES operations directly without requiring extra storage resources. This reduces the area occupied by the encryption system while maintaining security functions
3Reliability
If buffer storage and additional memory are used for IDE algorithms like AES-GCM, then data integrity and encryption can be achieved, but power consumption increases
Solution Approach 1:
The patent removes the need for buffer storage and additional memory components, thereby eliminating the power consumption associated with these resources. The streamlined architecture performs encryption/decryption operations more efficiently with lower power usage while maintaining data integrity protection
4Loss of time
If pre-calculating AES data is implemented, then latency is reduced, but the system must synchronize input data arrival with AES data readiness
Solution Approach 1:
The patent applies dynamics by implementing a flexible synchronization mechanism that adapts to varying data arrival rates and AES processing speeds. The system dynamically adjusts timing and control signals to ensure proper coordination between data input and cryptographic processing, managing complexity through adaptive rather than rigid synchronization
Data Source
AI summary
Technologies for providing integrity and data encryption (IDE) with zero latency are described. One receiving device with a cryptographic circuit having an Advanced Encryption Standard (AES) engine with a fixed epoch size and a fixed latency for IDE can send a delay parameter to a transmitting device. The delay parameter represents a number of clock cycles corresponding to the fixed latency. The cryptographic circuit can pre-determine, using the AES engine, AES data for a first epoch before first input data of the first epoch is received from the transmitting device. After the number of clock cycles, the cryptographic circuit can receive the first input data from the transmitting device. The cryptographic circuit can determine first output data for the first epoch using the AES data and the first input data without storing the AES data in a buffer.