Semiconductor Latency Counter Circuit With Fewer Control Bits
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Solution Overview
Problem
In semiconductor devices, particularly synchronous memory devices like DRAM, the latency in data transfer operations due to the need for analog mode operations and the use of latency counters to delay command signals limits the reduction of CAS latency and CAS write latency, leading to increased wiring density and power consumption as circuits are miniaturized.
Innovation Solution
A semiconductor device configuration that includes a first latency counter selecting odd-cycle latency and a second latency counter providing latency at intervals of two cycles, connected in series, reduces the number of control signal bits required, thereby decreasing wiring density and enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional latency counter using a shift register is used to delay command signals, then the required latency delay can be achieved, but the wiring density increases and circuit size increases
Solution Approach 1:
The latency counter is segmented into two functional units: a first latency counter that selectively provides odd-cycle latency (1, 3, 5, 7 cycles) and a second latency counter that provides latency at intervals of two cycles (2, 4, 6, 8 cycles). This segmentation allows the system to achieve any required latency value while using fewer control signal bits and reducing wiring density compared to a conventional shift register approach.
2Measurement precision
If the number of control signal bits is increased to provide precise latency control, then the latency control precision is improved, but the wiring density increases
Solution Approach 1:
The system dynamically selects between different latency paths based on control signals. The first latency counter uses a selector to choose between odd-cycle latency paths, while the second latency counter provides even-cycle latency. This dynamic selection mechanism enables precise latency control (any integer value from 1 to 8 cycles) while minimizing the number of control signal bits required and reducing wiring density.
Data Source
AI summary
For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.