Latency Counter Using Divided Clocks for High-Frequency Stability
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Solution Overview
Problem
Existing latency counters for synchronous memory devices face challenges in high-frequency clock operations, leading to synchronization issues and unstable ring counter states, resulting in count deviations and malfunctions, especially during self-refresh or power-down modes.
Innovation Solution
A latency counter design that utilizes a frequency-dividing circuit to generate divided clocks and frequency-divided counter circuits, allowing for stable latency counting even at high clock frequencies, with the option to add latency by one clock cycle, and using ripple counters to output binary count values, eliminating errors and enabling automatic restoration without restarting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ring counter is used to count latency in synchronous memory devices, then the latency counting function is achieved, but at high clock frequencies the ring counter becomes unstable and synchronization errors occur
Solution Approach 1:
The patent divides the single ring counter into multiple separate counter circuits, each handling specific latency counting tasks. This segmentation eliminates the instability issues of the traditional ring counter at high frequencies by distributing the counting function across multiple independent circuits that can operate reliably at higher clock speeds.
Solution Approach 2:
The patent introduces a control circuit as an intermediary that manages the multiple counter circuits. This control circuit coordinates the operation of the counters, handles reset signals, and ensures proper synchronization, thereby maintaining reliability while enabling high-frequency operation.
2Measurement precision
If different ring counters are used for input and output operations, then latency counting is achieved, but synchronizing the two counters becomes difficult at high frequencies leading to count deviations
Solution Approach 1:
The patent merges the input and output latency counting functions into a unified counter system under single control. By using multiple counter circuits that are coordinated by a control circuit rather than separate independent ring counters, the system maintains accurate latency measurement while avoiding synchronization problems at high frequencies.
Solution Approach 2:
The control circuit implements feedback mechanisms to monitor and adjust the operation of the counter circuits. This feedback ensures that the counters remain synchronized and accurate even at high clock frequencies, preventing count deviations and maintaining measurement precision.
3Device complexity
If the ring counter is shared between input and output uses, then device complexity is reduced, but the counter enters unstable states during self-refresh or power-down modes requiring full memory restart
Solution Approach 1:
Instead of sharing a single ring counter, the patent segments the counting function into multiple dedicated counter circuits. Each counter can be independently controlled and reset, preventing the instability that occurs when a shared counter enters self-refresh or power-down modes. This eliminates the need for full memory restarts while maintaining operational stability.
Solution Approach 2:
The control circuit provides self-service functionality by automatically managing the reset and coordination of the counter circuits during mode transitions. This self-management capability ensures reliable operation during self-refresh and power-down modes without requiring external intervention or system restart.
Data Source
AI summary
A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured.