Latency Counter Jitter Resilience via Timing Control
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Solution Overview
Problem
Existing latency counters in synchronous memory systems face challenges in maintaining latch margin due to jitter components in internal and external clocks, leading to reduced accuracy in measuring CAS latency.
Innovation Solution
A latency counter design incorporating a counter circuit and a point-shift FIFO circuit with timing control circuits and SR latch circuits to latch and reset internal commands, ensuring stable operation even with clock jitter, thereby maintaining latch margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a latency counter counts latency in synchronization with an internal clock generated by a DLL circuit, then the latency counting function is achieved, but the latch margin is reduced when jitter components exist in either the external clock or the internal clock
Solution Approach 1:
The patent introduces a timing control circuit as an intermediary between the counter circuit and the latch circuit. This timing control circuit generates a control signal based on the count value to precisely control the timing of latch operations, decoupling the direct synchronization dependency and providing buffer against jitter effects while maintaining measurement accuracy.
Solution Approach 2:
The timing control circuit performs preliminary action by generating control signals in advance based on predicted timing relationships. The control signal is generated before the actual latch operation occurs, allowing the system to prepare for potential jitter variations and maintain stable latch margins through proactive timing adjustment.
2Productivity
If the clock frequency is increased to increase data transfer rate, then productivity is improved, but the latch margin becomes more vulnerable to jitter components
Solution Approach 1:
The timing control circuit implements feedback by continuously monitoring the count value from the counter circuit and adjusting the control signal timing accordingly. This closed-loop approach allows the system to adapt to jitter variations in real-time, maintaining stable latch margins even at high clock frequencies where jitter effects are more pronounced.
Data Source
AI summary
A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.