Latency Counter SR Latch Reset Circuit
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Solution Overview
Problem
Existing latency counters in synchronous memory devices require complex reset circuits for each latch circuit, leading to increased circuit scale and power consumption due to the need for one-shot pulse generation for resetting.
Innovation Solution
A latency counter design that uses a point-shift FIFO circuit with SR latch circuits reset by a different count value from the counter circuit, eliminating the need for a reset circuit in each latch and reducing circuit complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset circuit is provided in each latch circuit to generate one-shot pulses for resetting, then the latch circuits can be reliably reset, but the circuit scale and power consumption increase
Solution Approach 1:
The reset function is extracted from individual latch circuits and centralized in a single reset circuit. The reset circuit generates a single reset signal that is distributed to all latch circuits, eliminating the need for complex reset circuits in each latch while maintaining reliable reset functionality.
Solution Approach 2:
A single reset circuit serves multiple latch circuits simultaneously. The reset signal generated by one circuit is universally applied to all latches, making the reset function multi-functional and reducing overall circuit complexity.
2Reliability
If a reset circuit is provided in each latch circuit to generate one-shot pulses for resetting, then the latch circuits can be reliably reset, but the power consumption increases
Solution Approach 1:
The power-consuming reset generation function is extracted from multiple individual latch circuits and consolidated into a single reset circuit, significantly reducing overall power consumption while maintaining the same reset reliability.
Solution Approach 2:
Multiple reset generation functions are merged into a single reset circuit. Instead of each latch having its own reset circuit, one reset circuit serves all latches, reducing redundant power consumption.
3Measurement precision
If each latch circuit includes a reset circuit for generating one-shot pulses, then the latency counting can be accurately controlled, but the overall circuit complexity increases
Solution Approach 1:
The reset signal generation function is extracted from individual latch circuits and centralized, simplifying the overall circuit structure while maintaining precise latency counting control through the centralized reset timing.
Data Source
AI summary
A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.