Latency-Driven Shared Buffer Algorithm for Network Switches

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing networking devices, such as switches, face challenges in efficiently managing shared buffers to minimize forwarding latency and ensure fair buffer allocation across multiple ports.

Innovation Solution

The implementation of a shared buffer system with dynamic binding of ingress ports to available portions of the shared buffer, based on proximity to associated egress ports, and a latency-driven algorithm for rebalancing and allocating buffer space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If packets are routed to the closest portion of the shared buffer to the egress port, then forwarding latency is reduced, but buffer allocation fairness among ports deteriorates

Engineering Contradiction:
Improveforwarding latencyVSAvoidbuffer allocation fairness
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The system implements a feedback mechanism where the shared buffer control system monitors buffer occupancy and allocation across all ports, and dynamically adjusts packet routing decisions. The forwarding database is updated based on real-time buffer status, ensuring that latency optimization for individual ports does not compromise overall allocation fairness. This closed-loop control resolves the contradiction by continuously adapting to system state changes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent employs dynamic buffer allocation where the binding between ingress ports and shared buffer portions is not static but adapts based on current buffer occupancy and traffic conditions. The system dynamically selects which port writes to and reads from which buffer block, allowing it to optimize latency when buffer resources are abundant while maintaining fairness when resources are constrained. This dynamic behavior resolves the contradiction between speed and fairness.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If a general shared buffer algorithm is used for buffer allocation, then device complexity is reduced, but forwarding latency increases

Engineering Contradiction:
Improvebuffer control complexityVSAvoidforwarding latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent applies local quality by associating specific portions of the shared buffer with specific egress ports based on physical proximity. Each port has a preferred buffer location optimized for its traffic patterns, reducing latency for local operations. The forwarding database maintains this local optimization information, allowing the system to achieve low latency without requiring complex global buffer management algorithms.

Inventive Principle:
Principle #3Local quality

3Loss of time

If dynamic binding of ingress ports to shared buffer portions is implemented, then forwarding latency is reduced, but device complexity increases

Engineering Contradiction:
Improveforwarding latencyVSAvoidbuffer management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system implements self-service through automatic buffer allocation and rebalancing. The shared buffer control system autonomously manages the dynamic binding between ingress ports and buffer portions, performing rebalancing operations based on buffer occupancy without requiring complex external control. This self-managing approach reduces latency through dynamic optimization while keeping the control mechanism relatively simple.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250165410A1Latency-driven shared buffer algorithm
Publication Date: 2025.05.22 MELLANOX TECHNOLOGIES LTD(IL)
  • US20250165410A1 patent drawing
  • US20250165410A1 patent drawing
  • US20250165410A1 patent drawing

AI summary

A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of portions, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit correlates egress ports with available portions among the plurality of portions as close as possible to a respective egress port.