Latency FIFO for Graphics Compute Power Management
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Solution Overview
Problem
Graphics processing systems face inefficiencies in energy management due to frequent enabling and disabling of computation stages, leading to power wastage and reduced performance per watt, primarily because of the fine-grained clock gating that results in high latency and underutilization of compute blocks.
Innovation Solution
Implementing a latency first-in/first-out (FIFO) memory that collects valid inputs and integrates invalid ones, allowing compute blocks to be enabled and disabled over a coarser time window, thereby reducing underutilization and improving energy efficiency by maintaining throughput demand over a time window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If fine-grained clock gating is used to disable computation stages, then energy consumption is reduced, but latency increases and compute blocks are underutilized
Solution Approach 1:
The patent merges multiple fine-grained clock gating control signals into a single coarse-grained control signal that manages the compute block as a unified entity. This consolidation reduces the frequency of enable/disable transitions and their associated latency penalties while maintaining energy efficiency through prolonged sleep states.
Solution Approach 2:
The system performs preliminary accumulation of ready inputs in a buffer before enabling the compute block. By preparing data in advance and batching multiple inputs together, the compute block can remain in sleep state longer without causing pipeline stalls, thus reducing both energy consumption and latency overhead.
2Loss of energy
If fine-grained clock gating is used to manage energy, then power efficiency improves, but compute block utilization decreases
Solution Approach 1:
The patent implements periodic enablement of the compute block based on accumulated input readiness rather than continuous or fine-grained periodic control. The compute block is enabled in sustained periods when multiple inputs are ready, creating a coarser periodic action pattern that improves utilization while maintaining energy efficiency through extended sleep intervals.
Solution Approach 2:
An intermediary buffering mechanism is introduced between input stages and the compute block. This buffer accumulates ready inputs and presents them in batches to the compute block, allowing the block to remain dormant longer and improve utilization when active, while the buffer absorbs the variability in input arrival patterns.
3Loss of energy
If frequent enable/disable transitions are implemented, then energy management is improved, but performance per watt decreases
Solution Approach 1:
The patent changes the temporal parameter of compute block control from fine-grained (per-input) to coarse-grained (batch-based). By modifying the enable/disable transition frequency and duration parameters, the system reduces the overhead of state transitions while maintaining effective energy management, thereby improving performance per watt.
Solution Approach 2:
The system maintains continuity of useful action by keeping the compute block in a sustained active state once enabled, processing multiple inputs in sequence without unnecessary disable/enable transitions. This continuous operation maximizes the utilization of the compute block's active state and avoids the performance penalty of frequent transitions, improving performance per watt.
Data Source
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AI summary
Techniques and architecture are disclosed for using a latency first-in/first-out (FIFO) to modally enable and disable a compute block in a graphics pipeline. In some example embodiments, the latency FIFO collects valid accesses for a downstream compute and integrates invalid inputs (e.g., bubbles), while the compute is in an off state (e.g., sleep). Once a sufficient number of valid accesses are stored in the latency FIFO, the compute is turned on, and the latency FIFO drains a burst of valid inputs thereto. In some embodiments, this burst helps to prevent or reduce any underutilization of the compute which otherwise might occur, thus providing power savings for a graphics pipeline or otherwise improving the energy efficiency of a given graphics system. In some instances, throughput demand at the latency FIFO input is maintained over a time window corresponding to the on and off time of the compute block