Latency-Guided Power Management Controller for Platform Energy Optimization

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Solution Overview

Problem

Conventional power management systems, such as those defined by the ACPI standard, fail to effectively reduce overall platform power consumption during idle periods due to longer wake-up times of non-processor components, leading to inefficiencies in power savings.

Innovation Solution

A power management system that includes a power management controller (PMC) dynamically generates a power management policy based on latency guidelines received from various components, allowing components to enter appropriate sleep states without adversely affecting performance, by considering their latency tolerance, quality of service, and other factors to optimize power savings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If non-processor components remain powered up to ensure better performance, then system responsiveness is improved, but overall platform power consumption increases

Engineering Contradiction:
Improvesystem responsivenessVSAvoidplatform power consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the power state of non-processor components based on real-time latency tolerance feedback from the operating system. Components transition between awake and sleep states adaptively, allowing the platform to optimize power consumption while maintaining responsiveness when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The operating system provides latency tolerance feedback to the power management controller, which uses this information to determine appropriate power states for non-processor components. This feedback mechanism enables the system to balance power savings with performance requirements effectively.

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If non-processor components enter sleep states to save power, then platform power consumption is reduced, but wake-up time increases

Engineering Contradiction:
Improveplatform power consumptionVSAvoidwake-up time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system dynamically selects sleep states and wake-up strategies based on the latency tolerance feedback received from the operating system. When latency tolerance is high, components enter deeper sleep states; when latency tolerance is low, components remain in lighter power states or stay awake, optimizing the balance between power savings and wake-up time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The power management controller proactively manages component power states based on predicted workload patterns and received latency tolerance guidance, preparing components to wake up at appropriate times to meet performance requirements while maximizing power savings during idle periods.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If processor enters deep sleep state C3 to save power, then processor power consumption is reduced, but time to return to execution state increases

Engineering Contradiction:
Improveprocessor power consumptionVSAvoidwake-up time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system dynamically determines the appropriate processor power state (C0, C1, C2, or C3) based on latency tolerance feedback from the operating system and current workload conditions, allowing the processor to optimize between power savings and quick resumption of execution.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The power management controller uses heuristics and received guidance to predict future processor activity and proactively manages processor power states, keeping the processor in lighter sleep states when quick wake-up may be needed and enabling deeper sleep states when extended idle periods are expected.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8176341B2Platform power management based on latency guidance
Publication Date: 2012.05.08 INTEL CORP
  • US8176341B2 patent drawing
  • US8176341B2 patent drawing
  • US8176341B2 patent drawing

AI summary

Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.