Latency Measurer With Correlation Headers For VoLTE

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Solution Overview

Problem

Current technologies face challenges in accurately measuring packet latency in IP-based communication networks, particularly in VoLTE services, which is crucial for network performance optimization and quality assurance.

Innovation Solution

The implementation of a latency measurer system that captures and tracks packets at various tapping points within an LTE Evolved Packet Core (ePC) network, using tapping points configured as software-defined network switches or hardware elements to wrap packets with correlation headers, allowing for latency measurement and analysis across different network segments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If packet latency measurement is implemented in IP-based communication networks, then network performance optimization and quality assurance are improved, but system complexity and implementation difficulty increase

Engineering Contradiction:
Improvepacket latency measurement accuracyVSAvoidmeasurement system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a latency measurer as an intermediary component that sits between the network elements and the measurement system. This measurer captures packets at tapping points, adds correlation headers with timestamps, and forwards them to a collector, thereby simplifying the overall measurement architecture while maintaining measurement accuracy

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates copies of packets at tapping points instead of analyzing original packets. These packet copies are wrapped with correlation headers and sent to the latency measurer, allowing measurement without interfering with the original network traffic flow and reducing the complexity of direct packet inspection

Inventive Principle:
Principle #26Copying

2Measurement precision

If multiple tapping points are deployed for comprehensive latency measurement, then measurement coverage and data quality improve, but network infrastructure complexity and cost increase

Engineering Contradiction:
Improvelatency measurement coverageVSAvoidnetwork infrastructure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The latency measurer is designed as a universal component that can collect data from multiple tapping points through a single collector interface. The correlation headers contain tapping point identifiers, allowing one measurer to handle measurements from multiple locations, thereby reducing the need for separate measurement systems at each tapping point

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple measurement functions into a single latency measurer component that aggregates data from various tapping points. The collector consolidates latency data from all tapping points into unified reports, reducing infrastructure complexity while maintaining comprehensive measurement coverage

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If real-time packet capture and analysis is performed, then network performance monitoring accuracy improves, but processing overhead and resource consumption increase

Engineering Contradiction:
Improvereal-time latency measurement accuracyVSAvoidprocessing resource consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the essential measurement data (packet copies with correlation headers containing timestamps and tapping point identifiers) from the full packet content. This extraction approach enables real-time measurement processing while minimizing the amount of data that needs to be analyzed, thereby reducing processing overhead and resource consumption

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10425308B2Latency measurer
Publication Date: 2019.09.24 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10425308B2 patent drawing
  • US10425308B2 patent drawing
  • US10425308B2 patent drawing

AI summary

In some described examples, a latency measurer receives packets from a tapping point. The packets may comprise wrapped packets including a wrapper header. The wrapper header may include a capture timestamp, a tapping point identifier, packet address and port information, and a message content hash.