Latency-aware Memory Controller with Priority Queues
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Solution Overview
Problem
Electronic devices with heterogeneous memory systems face challenges in prioritizing memory access across different memory regions with varying access latencies, leading to inefficiencies in access speed and energy consumption.
Innovation Solution
A memory controller is designed to schedule access to heterogeneous memory regions using multiple queues and access priorities, deferring high-latency commands to prevent bottlenecks and optimize throughput by prioritizing low-latency commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory access is prioritized without considering latency differences, then access speed improves, but energy consumption increases
Solution Approach 1:
The memory system is segmented into multiple memory regions with different access latencies. The controller divides memory access commands into different queues based on the target memory region's latency characteristics, allowing differentiated handling of high-latency and low-latency regions to optimize both speed and energy consumption.
Solution Approach 2:
The controller dynamically changes the priority parameter of memory access commands based on the latency characteristics of the target memory region. Low-latency commands are assigned higher priority and processed first, while high-latency commands are deferred, optimizing the balance between access speed and energy consumption.
2Productivity
If heterogeneous memory regions are accessed simultaneously, then throughput improves, but access priority management becomes complex
Solution Approach 1:
The command buffer is segmented into multiple queues (first queue for high-priority low-latency commands, second queue for low-priority high-latency commands). This segmentation simplifies priority management by providing clear separation between different command types while maintaining high throughput through parallel processing capability.
Solution Approach 2:
The controller dynamically switches between processing commands from different queues based on availability and priority. When low-latency commands are available, they are processed first; when only high-latency commands are available, the system switches to processing those, providing adaptive priority management that maintains throughput without excessive complexity.
3Device complexity
If high-latency commands are processed first, then queue simplicity improves, but access speed deteriorates
Solution Approach 1:
Instead of processing commands in the traditional first-in-first-out manner regardless of latency, the system inverts the priority logic by processing low-latency commands first and deferring high-latency commands. This inversion optimizes access speed for time-critical operations while maintaining a relatively simple two-queue structure.
Data Source
AI summary
A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.