Latency Offset Estimation for Clock Gate Circuits
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Solution Overview
Problem
In modern circuit design, the pre-Clock Tree Synthesis (CTS) stages rely on idealized clock signal latency, which can lead to overly optimistic latency values, causing computationally expensive re-positioning and re-specification during CTS, especially for clock gate circuits where the latency offset is not accurately estimated, affecting the timing of clock signals and power consumption.
Innovation Solution
The method involves estimating and applying latency offsets specifically for clock gate circuits during pre-CTS stages, allowing for more accurate time constraints on combinational logic, which improves the timing correlation and reduces computational resources by localizing latency effects, without impacting global clock latency values for other circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If idealized clock signal latency is used in pre-CTS stages, then timing evaluation is simplified and faster, but latency accuracy deteriorates leading to overly optimistic values
Solution Approach 1:
The patent performs preliminary latency offset estimation for clock gate circuits during pre-CTS stages, before the actual CTS process. This preliminary action provides more accurate latency values upfront, reducing the need for costly re-positioning later while maintaining evaluation speed.
Solution Approach 2:
The patent introduces latency offset as an intermediary parameter that mediates between the idealized global clock latency and the actual post-CTS latency. This offset value is estimated based on clock gate position and characteristics, providing a more accurate intermediate value for timing evaluation.
2Measurement precision
If accurate latency estimation is performed for clock gate circuits during pre-CTS stages, then timing correlation improves, but computational cost increases
Solution Approach 1:
The patent applies local quality by estimating latency offsets specifically for clock gate circuits rather than uniformly for all circuit elements. The latency offset is localized to individual clock gates based on their specific position and characteristics, providing accurate timing correlation only where needed without unnecessary computational overhead elsewhere.
3Measurement precision
If latency offset is applied to clock gate circuits, then enable path timing accuracy improves, but global clock latency values for other elements are impacted
Solution Approach 1:
The patent segments the clock latency into two distinct components: global clock latency that applies to all circuit elements, and localized latency offset that applies specifically to clock gate circuits. This segmentation allows the enable path timing accuracy to be improved for clock gates without impacting the global clock latency values used by other elements.
Data Source
AI summary
Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.