Latency Scheduling Mechanism for Register Pressure Bounded Sub-Blocks
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Solution Overview
Problem
Existing compiler technologies face challenges in balancing instruction scheduling for latency hiding with managing register pressure, leading to either excessive register demand or high compilation overhead, especially in Just-In-Time (JIT) compilation where dynamic optimization is required within a limited time budget.
Innovation Solution
A latency scheduler divides a code block into sub-blocks based on bounded register pressure thresholds and schedules each sub-block for processing, allowing for flexible latency hiding while controlling register demand, thereby reducing compilation overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If instruction scheduling is performed before register allocation to hide latencies, then latency hiding capability is improved, but register demand increases causing spills and performance degradation
Solution Approach 1:
The code block is divided into multiple sub-blocks with bounded register pressure, allowing the scheduler to work on smaller units that don't exceed register allocation limits while still achieving latency hiding across the entire block
2Productivity
If static compilation tracks register demand while scheduling instructions, then scheduling optimization is improved, but compiler complexity and compilation time increase due to backtracking
Solution Approach 1:
Register pressure bounds are predetermined and applied before scheduling begins, eliminating the need for backtracking and complex optimization loops while still enabling effective latency hiding through the sub-block division strategy
Data Source
AI summary
An apparatus to facilitate instruction scheduling is disclosed. The apparatus includes one or more processors to receive a block of instructions, divide the block of instructions into a plurality of sub-blocks based on a register pressure bounded by a predetermined threshold and instructions in each of the plurality of sub-blocks for processing.