Latency-Sensitive Task Scheduling via Core Usage Metrics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computing devices face challenges in managing latency-sensitive tasks efficiently, as processor cores become heavily loaded, leading to task stalls and perceived performance issues when interrupts are not timely resumed.
Innovation Solution
Scheduling latency-sensitive tasks based on processor core usage metrics, identifying heavily loaded cores, and reassigned tasks to more available cores to prevent suspension and ensure seamless execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor core is used to execute multiple tasks including latency-sensitive tasks, then the processor can handle more workloads, but the task execution time increases and latency-sensitive tasks may be suspended
Solution Approach 1:
The patent segments tasks by identifying latency-sensitive tasks and routing them to dedicated interrupt--free processor cores, while non-latency-sensitive tasks are executed on cores that can handle interrupts. This segmentation separates time-critical operations from general workloads, ensuring that latency-sensitive tasks are not suspended by interrupt handling while still utilizing multiple processor cores for overall productivity.
2Ease of operation
If interrupts are serviced immediately when received, then system responsiveness is improved, but latency-sensitive tasks experience suspension and execution delays
Solution Approach 1:
The patent introduces dedicated interrupt- free processor cores as intermediaries that handle latency-sensitive tasks exclusively. These cores act as mediators between the interrupt handling system and time-critical operations, isolating latency-sensitive tasks from interrupt interruptions while maintaining system responsiveness through proper interrupt routing to appropriate cores.
3Device complexity
If processor cores are assigned statically to tasks, then task scheduling is simplified, but processor core utilization efficiency decreases when cores become heavily loaded
Solution Approach 1:
The patent implements dynamic task routing where the scheduler monitors processor core load conditions and dynamically assigns latency-sensitive tasks to interrupt- free cores when available. This dynamic approach allows the system to adapt to changing workload conditions, maintaining simple scheduling logic for non-latency-sensitive tasks while providing specialized handling for time-critical operations when processor resources permit.
Data Source
Figure 1
Figure 2a
Figure 2b
AI summary
Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.