Programmable Device Latency Specification and Retiming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current programmable logic devices lack the ability to effectively optimize user logic designs for latency tolerance or sensitivity, which limits their operating speed and practicality in modern configurations.
Innovation Solution
The method involves accepting user inputs defining latency characteristics of user logic designs, determining configurations, and retiming them to maximize operating speed, using enhancements to hardware-description languages and graphical user interfaces to specify latency tolerance or insensitivity, allowing for the insertion of pipeline registers and optimization of circuit timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining is inserted to retine user logic designs, then operating speed is improved, but latency increases
Solution Approach 1:
The system dynamically adjusts pipeline register insertion based on user-specified latency tolerance. The configuration software allows users to define latency characteristics for different logic portions, and the tool selectively applies retiming and pipelining optimizations only where latency tolerance permits, creating a dynamic balance between speed optimization and latency constraints.
Solution Approach 2:
Different latency tolerance characteristics are applied to different portions of the user logic design. The system allows specific logic blocks to be marked as latency-tolerant or latency-sensitive, enabling localized pipelining optimization without uniformly increasing latency across the entire design. This selective approach allows speed improvement in tolerant regions while preserving timing constraints in sensitive regions.
2Productivity
If configuration software optimizes for maximum operating speed, then performance is improved, but complexity of configuration increases
Solution Approach 1:
The configuration software automatically performs retiming and pipeline register insertion based on user-specified latency characteristics. Users simply annotate their HDL code with latency tolerance information, and the software autonomously determines optimal register placement and configuration, eliminating the need for manual timing optimization while achieving maximum performance.
Solution Approach 2:
Manual timing optimization and manual pipeline register placement are replaced by automated configuration software that uses algorithms to determine optimal retiming. The software substitutes complex manual configuration processes with automated tools that analyze the design, apply latency constraints, and generate optimized configurations without requiring deep expertise in timing closure.
Data Source
AI summary
A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining latency characteristics of the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, and retiming the configuration based on the second user input.